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preliminary ver. 1.2.2 gigabitcam ke5bgca128
preliminary gigabitcam ke5bgca128 1. features 2. block diagram 3. pin assignment and pin de- scriptions 3.1 pin assignment 3.2 pin descriptions 4. functional descriptions 4.1 access from cpu port 4.2 read/write registers 4.3 access to the cam memory 4.4 search 4.5 data management by commands 4.6 restriction in pipeline operation 4.7 latency 5. connection 5.1 initialization 5.2 single device operation 5.3 cascade connection 5.3.1 device id registration 5.3.2 priority 5.3.3 cpu port in a cascaded system 5.3.4 output port in a cascaded system 6. command descriptions 6.1 command functions 6.2 command format 7. register descriptions 7.1 overview 7.2 register addresses 7.3 register bit maps 7.4 conditions for accessing regis- ters 8. package information 8.1 ordering information 8.2 package drawing 9. electrical characteristics 9.1 absolute maximum rating 9.2 operating range 9.3 dc characteristics 9.4 ac characteristics contents
1-1 preliminary gigabitcam ke5bgca128 1. features the ke5bgca128 provides best solution to the fast "ad- dress filtering" requirements of today's internetworking switching equipment with the following outstanding functions. ? 128k-bit capacity of table - 64-bit x 2048 entries - cam/ram substitution ? dual port architecture - 32-bit i/o port - 16-bit output port ? 12 search conditions -12 mask registers selected by the external pins (ms<3:0>) and the cntl1 register - access bit can be set for data aging - permanent bit can be set for permanent entry - automatic output of the contents of the hit entry and the empty entry address from the 16-bit output port ? cascading - table size is expandable. - a cascaded table acts as one integral search data table by internal device priority control. ? commands - useful commands for table management such as aging and purging. - useful command for source address learning ? synchronous operation - 30ns cycle time - 64-bit input/30ns - search, data read/write, and command operations are executed at high speed. ? 128-pin sqfp package ? 3.3 v cmos technology
2-1 preliminary gigabitcam ke5bgca128 64-bit x 2048 cam cntl1/2 registers memory r/w registers sconf register cmp1/2 registers hha/hea registers mask register 0~11 search logic control logic empty bit permanent bit access bit priority encoder decoder flag logic dat<31:0> clk phase phin phon pmin pmon flin flon oedatn output port control od<20:0> shon smon oeodn opsl srchn rwn cen rstn add<5:0> ms<3:0> cpu bus control pipeline execution control fig. 2 block diagram 2. block diagram this device consists of the following blocks as shown. cpu bus control block an access to the search key data, commands, or internal reg- isters are executed through the cpu bus. pipeline execution control this block controls the pipeline operation of this device. cntl1/2 registers these registers define the mask registers and the input modes , etc.
2-2 preliminary gigabitcam ke5bgca128 memory r/w registers these registers are used to access the cam table. sconf register this register defines the configuration of the search opera- tion. cmp1/2 registers these two registers store the search key data and both are 64 bits in width. hha/hea registers these two registers respectively store the hit address and the empty address of the cam table. mask registers these 12 registers are used to mask the data bit by bit in the search operation or the write operation to the cam table. cam the capacity of the cam table is 64 bits x 2048 entries. flag logic this block outputs the search result and the status of the cam table and has the interface function for a cascade connection. output port control this block controls the output port which outputs the search result.
3-1 preliminary gigabitcam ke5bgca128 38 39 1 128 103 65 64 102 index ke5bgca128 3. pin assignment and pin descriptions 3.1 pin assignment ke5bgca128 (128pin sqfp type) fig. 3.1.1 pin assignment
3-2 preliminary gigabitcam ke5bgca128 pin no . sign al name i/o typ e pin no . sign al name i/o typ e 1 gnd - 41 gnd - 2 od<0> out 42 pmon out 3 od<1> out 43 phon out 4vdd - 44flinin 5vdd - 45pminin 6 od<2> out 46 phin in 7 od<3> out 47 vdd - 8od<4>out 48 opsl in 9gnd - 49oeodnin 10 od<5> out 50 gnd - 11 od<6> out 51 gnd - 12 od<7> out 52 gnd - 13 gnd - 53 ms<0> in 14 od<8> out 54 ms<1> in 15 vdd - 55 ms<2> in 16 od<9> out 56 ms<3> in 17 od<10> out 57 dat<0> i/o 18 gnd - 58 dat<1> i/o 19 gnd - 59 vdd - 20 gnd - 60 dat<2> i/o 21 od<11> out 61 dat<3> i/o 22 vdd - 62 gnd - 23 od<12> out 63 dat<4> i/o 24 vdd - 64 dat<5> i/o 25 od<13> out 65 gnd - 26 od<14> out 66 dat<6> i/o 27 gnd - 67 dat<7> i/o 28 od<15> out 68 vdd - 29 od<16> out 69 vdd - 30 od<17> out 70 dat<8> i/o 31 od<18> out 71 dat<9> i/o 32 gnd - 72 gnd - 33 od<19> out 73 dat<10> i/o 34 vdd - 74 dat<11> i/o 35 vdd - 75 dat<12> i/o 36 od<20> out 76 gnd - 37 gnd - 77 dat<13> i/o 38 flon out 78 vdd - 39 smon out 79 dat<14> i/o 40 shon out 80 vdd - table.3.1 pin assignment
3-3 preliminary gigabitcam ke5bgca128 pin no . sign al name i/o typ e pin no . sign al name i/o typ e 81 phase in 121 cen in 82 clk in 122 rwn in 83 gnd - 123 srchn in 84 gnd - 124 oedatn in 85 gnd - 125 nc open*1 86 dat<15> i/o 126 gnd - 87 dat<16> i/o 127 gnd - 88 vdd - 128 gnd - 89 dat<17> i/o 90 dat<18> i/o *1 nc pins mu s t b e o pen . (do n ot con nect.) 91 dat<19> i/o 92 gnd - 93 dat<20> i/o 94 dat<21> i/o 95 dat<22> i/o 96 gnd - 97 dat<23> i/o 98 vdd - 99 vdd - 100 dat<24> i/o 101 dat<25> i/o 102 gnd - 103 dat<26> i/o 104 dat<27> i/o 105 gnd - 106 dat<28> i/o 107 dat<29> i/o 108 dat<30> i/o 109 dat<31> i/o 110 vdd - 111 add<0> in 112 add<1> in 113 add<2> in 114 add<3> in 115 gnd - 116 gnd - 117 gnd - 118 add<4> in 119 add<5> in 120 rstn in table 3.1 pin assignment (cont'd)
3-4 preliminary gigabitcam ke5bgca128 3.2 pin descriptions pin name attribute function clk clock input lvttl clk is the master clock input. other input signals are referred to the rising edge of clk. phase determines the action timing of the device. the latency of the output is also determined by the relationship between phase and clk. phase phase input lvttl regardless of whether the input mode is 32 bits (normal access mode) or 64 bits (first access mode), two cycles of the clk signals are necessary. phase regulates the input timing of the data input from 32-b it dat<31:0> when th e inp ut mo de is 64 b its . when phase is high, the data on dat<31:0> is input in the 32 bits on the msb side of 64 bits. when phase is low, the data is input in the 32 bits on the lsb side. when the input mode is 32 bits, the 32-bit data is written in the register designated by add<5:0> on the rising edge of clk while phase is low. dat<3 1:0 > cpu bus input/output tristate lvttl data<31:0> is a 32-bit, bidirectional data bus used to convey data, to execute commands, and to write/read to and from the registers. the direction is controlled by rwn and there is latency when the bus is switched. add<5:0 > cpu bus address bus input lvttl add<5:0> is a 6-bit address bus used to select registers. cen device enable input lvttl cen is used to access the cpu port. the active cen enables the input operation of data and command. rwn read/write input lvttl rwn is used to determine the direction of the cpu bus. rwn low selects a write cycle, and rwn high selects a read cycle. there is latency between the rwn change and the output as the result of the data bus change. oedatn cpu bus output enable input lvttl oeda tn co ntro ls the cpu b us ou tpu t. oeda tn low en ables th e output of the cpu bus by the read operation, and oedatn high makes the cpu bus have high impedance despite the output indication by the read operation. there is latency between the oedatn change and its result. srchn search enable input lvttl srchn enables the search operation together with the write operation to the comparand register.
3-5 preliminary gigabitcam ke5bgca128 pin name attribute function ms < 3 :0 > mask select input lvttl ms<3:0> is a mask select signal. one of 12 mask registers is selected by th e ms<3:0>. rs tn hardware reset input lvttl rstn is used to reset the hardware. od<20:0> output port ou tpu t tristate lvttl od<20:0> is a 21-bit output port. the device id is output in the 5 bits, od<20:16> from th e msb, and hha, hea, o r memhha is o utp ut in the 16 bits from the lsb. oeodn output port output enable input lvttl oeodn con trols th e outp ut po rt. oeodn lo w enab les the ou tpu t, and oeodn high disables the output (i.e. the output port is made high impedance). there is latency between the oeodn change and its result. opsl output port select input lvttl opsl low enables the output of memhha from the output port. there is latency between the opsl change and its result. shon s ynchronous hit output ou tpu t lvttl shon outputs the search results in the device synchronous with the master clock. this pin is low when even one hit occurs in the search operation. this pin is high when no entry is hit. smon s ynchronous multi-hit output ou tpu t lvttl smon outputs the search results in the device synchronous with the master clock. this pin is low when multi-hit occurs in the search operation. this pin is high when no multi-hit occurs. phon priority hit output ou tpu t lvttl phon outputs the search results. this pin is not synchronous with the master clock. this pin is low when even one hit occurs in the search operation. this pin is high when no entry is hit. in a cascaded system, the hit signal of the cascade configuration appears in the phon pin of the lowest priority device (last device). pmon priority multi-hit output ou tpu t lvttl pmon outputs the search results. this pin is not synchronous with the master clock. this pin is low when multi-hit occurs in the search operation. this pin is high when no multi-hit occurs. in a cascaded system, the multi-hit signal of the cascade configuration appears in the pmon pin of the lowest priority device (last device).
3-6 preliminary gigabitcam ke5bgca128 pin name attribute function phin priority hit input input lvttl phin is used to connect plural devices in a cascaded system. pmin priority multi-hit input input lvttl pmin is used to connect plural devices in a cascaded system. flon full flag output ou tpu t lvttl flon outputs the search results. this pin is low when all entries in the cam are filled with valid entries (full status) and there is no more entry for a new registration. in a cascaded system, the full signal of the cascade configuration appears in the flon pin of the lowest priority device (last device). flin full flag input input lvttl flin is used in a cascaded system. vdd s uppl y po wer s up ply : 3.3v0.3v gn d (s uppl y) gr ou nd ground
4-1 preliminary gigabitcam ke5bgca128 4. functional descriptions 4.1 access from cpu port this device has a 32-bit data bus as a cpu port. data read/ write is performed by the registers that are mapped with 32- bit width (refer to chapter 7.2). to access registers wider than 32 bits or to access the cam memory, two data read/ write accesses are required. a special high speed write mode (fast write mode) is provided for the data write. ? normal access mode in this mode, one 32-bit data read/write is done with one phase signal cycle. data, address and control signals must be input synchronously with the rising edge of clk when the phase signal, which is a double cycle signal of the clk, is low. (see fig. 4.1.1 (a)) all the bits of each register address are valid in this mode. each 32-bit register is defined by the address pins add<5:0>. two accesses cycles are required for the read/ write of 64-bit registers and the cam memory. dat<31:0> clk phase rwn add<5:0>,cen ms<3:0>, srchn setup hold setup hold setup hold setup hold setup hold data write (32bits) data read (32bits) input operation dat read latency=4 <63:32> or <31:0> <63:32> <31:0> or min. 15ns fig. 4.1.1 (a) cpu access mode (normal access mode)
4-2 preliminary gigabitcam ke5bgca128 ? fast write mode in this mode, one 64-bit data read/write is done within one phase signal cycle. the upper 32-bit data of the 64-bit reg- ister is input synchronously with the rising edge of clk when the phase signal, which is a double cycle signal of the clk, is high. the lower 32-bit data of the 64-bit register, address, and control signals are input synchronously with the rising edge of the clk signal when the phase signal is low. (see fig. 4.1.1 (b)) the lsb of the address is ignored in this case. if a 32-bit register is accessed in this mode, only the data, the address, and the control signals that are input with the rising edge of clk while the phase signal is low, are valid. (see fig. 4.1.1 (b)) the lsb of the address is also ignored in this case. normal access or fast write mode is selected by the defi- nition of the cntl1 register. the initial definition after the device reset is normal access mode. fig. 4.1.1 (b) cpu access mode (fast write mode) clk phase dat<31:0> rwn add<5:1>,cen ms<3:0>, srchn setup hold setup hold setup hold setup hold setup hold setup hold data write (64bits) data write (32bits) <63:32> <31:0> <31:0> min. 15ns operation input
4-3 preliminary gigabitcam ke5bgca128 fig. 4.2.1 data read/write timing chart (fast write mode) 4.2 read/write registers the register address is designated by the address pins of the cpu port, and the data is inputted on the dat bus. (see fig. 4.2.1) the function of each register is described in chap- ter 7. this figure shows the example of the fast write mode. in case of the normal access mode, data write is the same as the fast write mode shown in fig. 4.2.1 if you exclude the write of the upper 32 bits of the 64-bit word. cen clk phase data write (64bits) input operation rwn ms<3:0> srchn add<5:0> dat<31:0> data write (32bits) data read (32bits) data read (32bits) data write (64bits) data read (32bits) data read (32bits) wait data write (32bits) data write (32bits) wait min. 15ns <63:32> <31:0> <31:0> <31:0> <63:32> or<31:0> <63:32> or<31:0> <31:0> <63:32> or<31:0> <31:0> <63:32> or<31:0> *1)64bits data write *1) dat read latency=4 dat read latency=4 <63:32>
4-4 preliminary gigabitcam ke5bgca128 fig.4.3.1 word structure of cam permanent bit access bit empty bit content 64 bits 1bit 1bit 1bit 4.3 access to the cam memory ? word structure of cam one word of the cam is made up of 64-bit cam memory and 3 attribute bits (1 bit each). the 64-bit cam memory stores the users data to be searched. the attribute bits are the empty bit, the permanent bit, and the access bit. (see fig. 4.3.1): the empty bit: the empty bit is a flag that indicates the validity of the cam word. an invalid word is excluded from the search target and is recognized as a candidate for memory for a new registration of valid data. the flag logic is: 0 : valid (valid data is written); 1 : invalid (memory is a space). the permanent bit: the entry whose permanent bit is set to "1" will not become invalid (empty bit = 1) by any purge commands. in order to clear this bit, users can use the reset command. the access bit: the access bit is provided for the manage- ment of the hit career of each entry. users can specify whether the hit career is held in the access bit or not for each search cycle. once the access bit is set to "1," how- ever, it holds "1" until an access bit reset command is ex- ecuted. these attribute bits can be directly modified by accessing the memar_at, memhha_at, and memhea_at registers. these bits are reset by the reset signal from the rstn pin as follows: ? the empty bit : 1 (invalid) ? the permanent bit : 0 (impermanent) ? the access bit : 0 (no hit career)
4-5 preliminary gigabitcam ke5bgca128 ? read/write cam memory read/write of the entry data is executed not by direct ad- dress indication, but by indirect address indication through specific registers (memar, memarai, memar_at, memhha, memhha_at, memhea, memheaai, and memhea_at). when writing through memar, memarai, memhha, memhea, and memheaai, 12 kinds of mask conditions can be selected. mask in the data write operation means that the data of masked bit is not changed by the write operation. there are two ways to se- lect the mask condition from the 12 mask registers (mask0 - mask11). one way is to select it with 4 single pins, ms<3:0> applied dynamically in data write. the other way is to select by the definition in the cntl1 register statically . the read/write of the cam memory is basically the same as the read/write of the registers. as shown in fig. 4.2.1, the mask condition in the write operation is selected by ms<3:0>, the status of these select control signals is latched by the rising edge of clk while the phase signal is low, and the data is written to the memory with latency 2. the read data is output from the cpu port with latency 4. (see section 4.7 about latency.) ? read/write cam data through the memar register read/write operation of the cam word, whose address is designated by the ar register, is executed by the memar register. write through the memar register changes the attribute bits in the cam word as follows: ? empty bit : 0 (entry is valid.) ? permanent bit : return to the default value defined in the cntl1 register ? access bit : return to the default value defined in the cntl1 register. ?read/write cam data through the memarai register read/write operation of the cam word, whose address is designated by the ar register, is executed by the memarai register. one read/write to the memarai reg- ister increments the value of the ar register automatically. write through the memarai register changes the at- tribute bits in the cam word as follows: ? empty bit : 0 (entry is valid.) ? permanent bit : return to the default value defined in the cntl1 register. ? access bit : return to the default value defined in the cntl1 register. ?read/write cam data through the memhha register read/write operation of the cam word, whose address is designated by the hha register, is executed by the memhha register. read/write through the memhha register is prohibited when the address stored in the hha register is invalid, because this may cause an access to the undesired cam word and the data in it might be destroyed. read/write through the memhha register does not change the attribute bits in the cam word.
4-6 preliminary gigabitcam ke5bgca128 ?read/write cam data through the memhea register read/write operation of the cam word, whose address is designated by the hea register, is executed by the memhea register. read/write through the memhea reg- ister is prohibited when the address stored in the hea reg- ister is invalid, because this may cause an access to the undesired cam word and the data in it might be destroyed. write through the memhea register changes the attribute bits in the cam word as follows: ? empty bit : 0 (entry is valid.) ? permanent bit : return to the default value defined in the cntl1 register. ? access bit : return to the default value defined in the cntl1 register. ?read/write cam data through the memheaai register read/write operation of the cam word, whose address is designated by the hea register, is executed by the memheaai register. one read/write to the memheaai register shifts the value of the hea register to the value of the next hea automatically. write through the memheaai register changes the attribute bits in the cam word as follows: ? empty bit : 0 (entry is valid.) ? permanent bit : return to the default value defined in the cntl1 register. ? access bit : return to the default value defined in the cntl1 register. ?read/write cam data through the memar_at, memhha_at, and memhea_at registers read/write operation to the attribute bits of the cam word, whose address is designated by the ar, the hha, and the hea registers respectively, is executed by these registers. examples of this operation would be to make the designated cam word invalid, to make the designated cam word per- manent, and/or to change the access bit of the designated cam word. users can mask each attribute bit. (refer to chapter 7 for more details.) this capability also enables the attribute of the cam word to be read.
4-7 preliminary gigabitcam ke5bgca128 fig. 4.4.1 srch operation through cmp register write 4.4 search ? search operation through the cmp1/2 regis- ter the key data should be written to the cmp1/2 register from the cpu bus. the low pulse of the srchn pin synchro- nized with the rising edge of clk while the phase signal is low activates the search operation when the key data is written. the mask condition for the search is also chosen from 12 kinds of mask conditions defined by the mask registers (mask0 - mask11), dynamically by the status of the ms<3:0> pins or statically by the cntl1 register. the cmp1/2 register stores the key data until the next write operation is done. users can choose to perform a search operation in the normal access mode or the fast write mode. the example is shown in fig. 4.4.1 (a/b). in fig. 4.4.1, the search operation is started by the data write to the cmp1/2 register and the synchronous low pulse to the srchn pin. as a result, the hit flag is output on the shon pin with latency 4, the multi-hit flag is output on the smon pin with latency 5, and the hha and the devid of the device which has a hit are output on the od<20:0> with latency 5. fig. 4.4.1 shows two methods for searching the cam. in this example, the first search is executed by a pulse from the srchn pin using the data previously written to the cmp1/2 register. the second search operation is ex- ecuted by the command, srch 1/2. this time, the search operation by command is executed with the data already written in the cmp1/2 register used in the previous search. cen clk phase srch rwn ms<3:0> srchn add<5:0> dat<31:0> data write (32bits) min. 15ns <31:0> (or<63:32>) <63:32> (or<31:0>) shon smon od<20:0> <31:0> com (srch) (a) normal access mode operation input latency shon: 4 (or 5) smon: 5 od (hha, devid): 5 (or 6, 7, 4) oeodn
4-8 preliminary gigabitcam ke5bgca128 fig. 4.4.1 srch operation through cmp register write cen clk phase rwn ms<3:0> srchn add<5:1> dat<31:0> srch <31:0> <31:0> <63:32> com (srch) (b) fast write mode operation input min. 15ns shon smon od<20:0> latency shon: 4 (or 5) smon: 5 od (hha, devid): 5 (or 6, 7, 4) oeodn
4-9 preliminary gigabitcam ke5bgca128 fig. 4.4.2 srch operation with command ? search operation by commands the search command, srch 1/2, written to the command register (com register) activates the search operation using the key data stored in the cmp1/2 register. the mask condition for the search is chosen at the time of command write from 12 kinds of mask conditions defined by the mask registers (mask0 - mask11). the mask regis- ter is chosen dynamically by the status of the ms<3:0> pins on the rising edge of the clk signal while the phase signal is low or statically by the cntl1 register. like the search operation above, users can choose the write mode from the normal access mode or the fast write mode. in both modes, the search operation is started by the command (srch). the example is shown in fig. 4.4.2 (a/b). cen clk phase input operation rwn ms<3:0> srchn add<5:0> dat<31:0> data write (32bits) min. 15ns <31:0> (or<63:32>) <63:32> (or<31:0>) <31:0> com (srch) (a) normal access mode data write (32bits) shon smon od<20:0> latency shon: 4 (or 5) smon: 5 od (hha, devid): 5 (or 6, 7, 4) oedon
4-10 preliminary gigabitcam ke5bgca128 fig. 4.4.2 srch operation with command cen clk phase input operation rwn ms<3:0> srchn add<5:1> dat<31:0> <31:0> <31:0> <63:32> shon smon od<20:0> com (srch) (b) fast write mode data write (64bits) min. 15ns oeodn latency shon: 4 (or 5) smon: 5 od (hha, devid): 5 (or 6, 7, 4)
4-11 preliminary gigabitcam ke5bgca128 ? access bit set while searching when a hit occurs in the cam word while searching, the hit result of the entry can be stored as the access bit data. this means the past career of the hit results can be man- aged. for every 12 mask registers, the determination of whether the search result is stored in the access bits or not (whether the access bits must be set according to the hit result) can be done using the sconf register. (refer to chapter 7 for more details.) ? search result flag pins (phon, pmon, shon, smon) the phon and shon pins indicate if the hit word (the cam word which is hit) exists. a high level on the phon pin indicates that a single hit does not exist and a low level on this pin indicates that a single hit exists and multi-hit does not exist. a high level on the shon pin indicates that no hit exist and a low level on this pin indicates that a single hit or multi-hit exist. the phon pin goes to an unknown status when the search operation starts, and it outputs high or low level according to the search result. the phon pin outputs the search results asynchronously with the clk. the shon outputs the corresponding search result syn- chronously with clk. (see fig. 4.4.2. refer to chapter 5 for more details) the pmon and smon pins indicate if multi-hit entries exist. a high level of these pins indicates that a multi-hit does not exist and the low level of this pin indicates that a multi-hit exists. the pmon and smon pin goes to an un- known status when the search operation starts, and it out- puts high or low level according to the search result the pmon pin outputs the search results asynchronously with the clk. the shon outputs the corresponding search re- sult synchronously with clk. (see fig. 4.4.2.) hha register the hha register stores the address of the cam word that is hit by the search operation. the hha register has the valid bit that indicates the validity of the data stored in the hha register. this valid bit becomes 0 if single hit (no multi-hit word exist) exists. if a multi-hit or no hit exists, the valid bit becomes 1 , invalid. the hha register also stores the data output to the phon and pmon pins accord- ing to the search result, namely hit and multi-hit flag data (labeled syh and sym in section 7.3 register bit maps). in a cascaded system in which multiple devices are intercon- nected, the last device in the chain holds the hit and multi- hit flags of the total system. careful consideration is required for the hha register, be- cause the hha (highest hit address) becomes invalid data when a multi-hit exists. the search configuration register, sconf, allows the user to set the access bit according to the search operation results. even though a multi-hit is set as invalid, all the access bits of hit words are still set. hit and multi-hit status of the total system is valid only when the hha register in the last device is accessed with the timing which considers the propagation delay between the devices. memhha register the memhha register is used to read and write the hit cam. the mask condition in the 12 mask registers is also used for a partial write to modify part of the hit cam word. the write through the memhha register is prohibited when the address stored in the hha register is invalid, be- cause this may cause access to the undesired cam word and the data in it might be destroyed.
4-12 preliminary gigabitcam ke5bgca128 fig. 4.4.3 output port format opsl = 1 20 16 15 14 11 10 0 hha or hea devid hha/hea fla g 0: hha 1: hea valid flag 0: valid 1: invalid 20 16 15 devid opsl = 0 0 part of memhha ke5bgca128 od<20:0> output from output port the output port is a 21-bit output bus used for the search result. the main purpose of this port is to output the hha. usually, 5 bits out of the 21 indicate the device id (the id data provided to recognize the device in the system with multiple devices), and the other 16 bits output the hha that indicates the hit address in the device. the output port is controlled by the oeodn pin. the hha, the hea, and part of the memhha (16 bits) can be output from the output port. the sconf register defines which data set listed above will be output. the sconf register holds the following 5-bit information for each of the 12 mask conditions. these bits determine what kind of search result is output from the output port, caused by the corresponding mask condition: as* (1bit): whether the access bits are set or not he* (1bit): whether the hea is output or not when no hit mh* (1bit): whether part of the memhha is output or not s*<1:0> (2bits): which part of the memhha is output 00: memhha<15:0>, 01: memhha <31:16>, 10: memhha<47:32>, 11: memhha<63:48> (* : 00 - 11) the output data selection with the opsl pin is necessary to output the memhha. (see fig. 4.4.3)
4-13 preliminary gigabitcam ke5bgca128 fig. 4.4.4 output latency of srch operation the latency (how many clock cycles of delay from the data input) can be defined by the cntl2 register. the latency of the hha output (or the hea output) can be selected from 4, 5, 6 and 7. the latency of the memhha output can be selected from 6 and 7. (see fig. 4.4.4) if the output port is connected to the same bus in a cas- caded system, the output control with the oeodn pin or with the latency selection is required so that the bus conflict does not occur. (refer to chapter 5 for more details.) ? definition of the mask register for search and write ke5bgca128 has 12 mask registers. there are two meth- ods of mask selection for each of the four register groups. one way is to select it dynamically with ms<3:0> pins. the other way is to select it statically by the definition in the cntl1 register. the registers are broken up into four groups as follows: a group: the search (or write) with the cmp1 or cmp2 register b group: the search with the srch1 command or the srch2 command cen, rwn clk phase input operation ms<3:0>, add<5:0> srchn dat<31:0> srch (a) latency :4 <63:32> shon smon od<20:0> latency min. 15ns <31:0> 1 2 3 4 5 6 7 (b) latency :5 latency :5 memhha (a) latency :6 (b) latency :7 hha(or hea)& devid (a) latency :4 (b) latency :5 (c) latency :6 (d) latency :7 opsl opsl
4-14 preliminary gigabitcam ke5bgca128 c group: the write with the str commands d group: the write with the mem registers each of these groups has one bit in the cntl1 register that is used to define the method of selection, either from the pin ms<3:0>, or from the register. if the mask condition is se- lected from the register, there are four bits for each group in the cntl1 register that selects one of the 12 mask regis- ters. (refer to chapter 7 for more details.) if the mask condition is defined to be selected by the pins, following bits corresponds to each mask register. the data of ms<3:0> pins should be input synchronously with the rising edge of clk when the phase signal is low level as described above. ms<3:0> pins mask register 0000 mask 0 register defines the mask condition. 0001 mask1 register defines the mask condition. 0010 mask2 register defines the mask condition. 0011 mask3 register defines the mask condition. 0100 mask4 register defines the mask condition. 0101 mask5 register defines the mask condition. 0110 mask6 register defines the mask condition. 0111 mask7 register defines the mask condition. 1000 mask8 register defines the mask condition. 1001 mask9 register defines the mask condition. 1010 mask10 register defines the mask condition. 1011 mask11 register defines the mask condition. if the bit of the mask register is 1, the bit is dont care and not searched. if the bit of the mask register is 0, the bit is "care" and searched. one of the 12 mask registers must always be defined in the search operation. mask registers are also used for the mask condition of the write operation to the cam memory. if the mask is set (the bit is 1.), the corresponding bit of the cam memory is not changed by the write operation. one of the 12 mask regis- ters must always be defined in the write operation. 4.5 data management by commands ke5bgca128 has several commands for data management. this chapter describes the important points. (refer to chap- ter 6 for more details.) ? data management using access bits the following three commands are provided regarding the access bits: prg_ac: erases all the cam words whose access bits are 1. prg_nac: erases all the cam words whose access bits are 0. rst_ac: clears all the access bits (access bit: 0). an example of using these commands would be to perform a search with the definition that the hit career is being held in the access bit, then delete unnecessary cam words whose access bits are 1 (or 0). another example is to delete all the cam words which hit (or did not hit) after the search with certain data. ? data management using store commands str1/2_hha command this command overwrites the data of the cmp1/2 register to the hit cam word using the mask condition of the defined mask register. in other words, this command is a partial (maskable) write to the hit address, and it is useful for time stamping to the cam word. the time stamping data can be used, for example, to find the oldest cam words by search- ing this, and delete them.
4-15 preliminary gigabitcam ke5bgca128 fig. 4.5.1 str1/2_aut command operation clk phase input operation execute0 pinout hha execute1 output2 (od) pinout srch shon execute0: srch operation execute1: hha output operation from the od bus shon/smon latency:5~7 decode & setup operation request (cpu) str1/2 _aut decode & setup operation request (cpu) wait/nop execute wait str1/2_hea command this command overwrites the data of the cmp1/2 register to the empty cam word using the mask condition of the defined mask register. in other words, this command is a partial (maskable) write to the empty address, and it is use- ful to register new cam word data when there is no hit cam word in the search. the commands str1/2_hha and str1/2_hea should be executed according to the search result. ke5bgca128 op- erates with the pipeline method synchronously with the ex- ternal system clock causing multiple steps of latency before receiving the results of each operation. if the command is executed after receiving the result of each operation, it will affect the performance. s tr1/2_aut command to avoid the performance problem described above, the str1/2_aut command is provided in this device. this command executes the same operation as the str1/ 2_hha command if the device has a hit, and executes the
4-16 preliminary gigabitcam ke5bgca128 same operation as the str1/2_hea command if the device does not have a hit. users can execute this command re- gardless of whether the device has a hit or not, so that the overhead caused by the unnecessary judging cycles can be reduced. the example is shown in fig. 4.5.1. the status of the internal pipeline is also shown in the example. (refer to chapter 4.6 for more details.) the str1/2_aut command is executed one wait after the external request for the search. the one wait in this example is inserted because the idle time of one phase signal is necessary to utilize the search result infor- mation such as a hit. however, the str_aut command should only be used when the cascade connection uses external logic. (refer to chapter 5 for more details.) for these str commands, users can use the mask condition defined by ms<3:0> pins or the cntl1 register. when using the cntl1 register, this would be group c. 4.6 restriction in pipeline operation ke5bgca128 is designed to use a maximum main clock of 66 mhz. this clock is synchronized with external requests, resulting in operations which are processed by the internal pipeline. internal pipeline processing has several stages corresponding to various requests for operation. when us- ers request multiple operations continuously from the out- side, these operations must be requested so that a conflict between the pipeline stages does not occur. this chapter describes the ways the internal pipeline stages work to process the external request, and the rules for continuous input of the various operations. ? stages of pipeline the following are five groups of stages of the pipeline for the operation request: (1) operation request stage in this stage, the operation is requested through the cpu bus, with the data and the address input being latched. there are two kinds of stages, read request stage and write request stage. the difference between these two stages de- pends upon whether the dat bus is occupied. the read request stage does not occupy the dat bus, but the write request stage occupies the dat bus. (2) decode & setup stage this stage follows the operation request stage. the data or the address that is latched in the operation request stage is decoded to recognize the request, and then the necessary data is set up in this stage. (3) execute stage in this stage, the external request for operation is executed. there are two kinds of operations, the operations that can be executed with the other pipeline stage, see fig. 4.5.1, and the operations that cannot be executed with the other pipe- line stage, according to which block in the device is ex- ecuted. (4) wait/nop stage this stage is for the timing adjustment of the internal bus driving. (5) output stage two stages, output1 and output2, are included. output1 is the stage for the output of the dat bus, and output2 is the stage for the output of the od bus. output1 and output2 can be executed simultaneously because these ports, dat bus and od bus, are different ports. ? processing and pipeline stages the following seven types are the categories of operation according to the pipeline stages:
4-17 preliminary gigabitcam ke5bgca128 fig. 4.6.1(a) pipeline operation stage chart phase latency clk decode & setup execute0 wait/nop execute2 decode & setup execute decode & setup execute execute decode & setup execute wait/nop output1 (cpu) decode & setup execute output1 (cpu) pinout output2 (od) shon hha execute1 output2 (od) shon/smon hha output2 (od) hha output2 (od) wait/nop 1) with hha out p ut 2) with memhha output output2 (od) a) b) c) wait/nop wait/nop wait/nop wait/nop wait/nop pinout execute1 execute1 execute2 hha latency : 5 decode & setup execute decode & setup execute wait/nop output1 (cpu) execute0: srch operation execute1: hha output operation from the od bus execute2: memhha output operation from the od bus operation request(cpu) operation request(cpu) operation request(cpu) operation request(cpu) operation request(cpu) operation request(cpu) operation request(cpu) hha latency : 6 hha latency : 7 a) b) memhha latency : 6 memhha latency : 7 memhha memhha type 7 : srch operation with hha output type 1 : register write operation type 3 : register (except hha/hea) read operation type 5 : 2-cycle command operation type 6 : hha/hea register read operation type 2 : mem write or 1-cycle command operation type 4 : mem read operation 5 6 7 4 1 2 3 high low high low high low
4-18 preliminary gigabitcam ke5bgca128 type1: registers write operation or 1 cycle command operation type2: mem* write operation *1 type3: registers (except hha and hea) read operation type4: mem* read operation *1 type5: 2 -cycle command operation *2 type6: hha/hea register read operation type7: srch operation with hha read (with hea read) *1): the read/write of the memheaai register is in type5. *2): srst, gen_fl, nxt_he, str1_heaai, str1_autai, str2_heaai, str2_autai commands the pipeline stage timing of each type is shown in fig. 4.6.1. as shown in fig. 4.6.1(a), the operation request stage in type 1, 2, 7 is divided into two stages (high and low) because the 64-bit data could possibly be written to the register or to the cam word using the fast write mode (64- bit access per one phase signal cycle). ? restriction of simultaneous execution of pipeline stages there are some restrictions of simultaneous executions of the internal pipeline stages. basically, the simultaneous ex- ecution of the different pipeline stages is possible if they are in different pipelines, but the simultaneous execution must meet the following restrictions: 1) the write request of the operation request stage and the output1 stage must not be executed simultaneously because they use the same bus (dat bus). 2) any operation can execute simultaneously during wait/nop stages. 3) the possible simultaneous operations of the execute stages between the multiple pipelines are restricted to the following 3 cases: a) the execute of type5 and the execute of types 1- 7 b) the execute of type6 and the execute of types 1- 7 c) the execute1 and the execute2 of type7 and the execute of types 1- 6 these executions must follow the restriction shown in table 4.6.1. the column of the table 4.6.1 means execute stage which is possible to simultaneously execute. as shown in fig. 4.6.1 (b), the the column of the table means 1st input operation, and the row of the table means 2nd input operation. clk phase input operation 1st input operation 2nd input operation fig. 4.6.1(b) restriction of pipeline
4-19 preliminary gigabitcam ke5bgca128 with memhha output type 1 : register write operation type 3 : read operation 2-cycle command operation, memheaai type 6 : hha/hea register read operation type 2 : mem_hha, _hea, _ar, _arai write or 1-cycle command operation type 4 : mem_hha, _hea, _ar, _arai with hha output with memhha output type 7 : srch operation type 5 : 2-cycle command operation *4) type 6 : hha/hea register read operation type 7 : srch operation with hha output *2) *3) *3) x read operation register (except hha/hea) type 5: 1st input operation 2nd input operation *1) *5) *6) *6) *1) only the nxt_he command and mem write can be simultaneously executed. *2) impossible to simultaneously execute with the execute 0 of the srch operation. *3) impossible to simultaneously execute with the write to the cntl2 register. *4) in case of the srst command, reset operation has priority. *5) execute of the hea read operation cannot be simultaneously executed execute of the gen_fl, nxt_he, str1/2_heaai, str1/2_autai (mis-hit case), and memheaai access. *6) execute of the hha read operation cannot be simultaneously executed execute of search operation. table 4.6.1 restriction of pipeline : allowed : allowed partially : not allowed x x x x x x x x x
4-20 preliminary gigabitcam ke5bgca128 fig.4.6.2 restrictions between data read/write operations ? restriction in usage of the result of data operation in each pipeline data write and read the write and read operations of the data are classified into type1/2 and type3/4. as shown in fig. 4.6.2, data write (2), (3) input operation can be put on after data read input operation to use pipeline of the device effectu- ally. however, (4) ~ (5) input operation stage cannot be used because data output of data read (1) starts on the wait stage (5). definition of search condition and search operation the search operation can executed immediately after the search condition has been changed with the write to the cntl1 register , the mask register, or to the sconf regis- ter. it is not possible to change the output latency during the search operation. the search condition (latency) must be kept unchanged until the output operation of the search result has been completed (see fig. 4.6.4). the output latency is defined in the cntl2 register. clk phase input operation execute decode & setup data write execute decode & setup wait/nop output1 (cpu) execute decode & setup operation request(cpu) operation request(cpu) operation request(cpu) data read data write data write operation request(cpu) execute & setup decode wait wait wait (1) (2) (3) (4) (5) (6)
4-21 preliminary gigabitcam ke5bgca128 search and use of the search result for continuous operations executed through the cpu, some operations are restricted. these types of operations must be executed according to the result of the previous opera- tion. an example would be when reading the hha through the cpu port using the memhha register after the search operation. using this example, the restriction of the usage of the result of data processing is described. as shown in fig. 4.6.1, the hha is determined in the wait/nop stage, one cycle after the execute0 stage for a search operation which is type7. if the reading of the memhha is requested right after the request of the search operation, as shown in fig. 4.6.3 (a), the execute of the read operation of the memhha is executed at the same time as the wait/nop stage of the srch. the value in the hha has not been decided yet, so this execute is not executed correctly. this is because the reading operation of the memhha uses the hha. in the cases as above, one wait is necessary before an operation which uses the hha, such as the request for reading the memhha register (see fig. 4.6.3 (b).). if the search is per- formed after an operation which uses the hha, such as reading the memhha register, one wait is not necessary. change the hea and use of the hea in the same way as the hha, two waits are necessary before an operation which uses the hea, such as the request for reading the memhea register (see fig. 4.6.3 (c).). if an operation which changes the hea is performed after an operation which uses the hea, two waits are not necessary. operations which change the hha or the hea and operations which use the hha or the hea the operations which change the hha or change the hea and the operation which use the hha or use the hea, are listed as follows. operations which change the hha search operation with the srchn pin srch1/2 command operations which change the hea memheaai register access gen_fl, nxt_he, str1/2_heaai, str1/2_autai commands operations which use the hha memhha register access str1/2_hha, str1/2_aut (hit case), str1/2_autai (hit case) commands operations which use the hea memhea register access memheaai register access str1/2_hea, str1/2_aut (mis-hit case), str1/2_autai (mis-hit case) commands
4-22 preliminary gigabitcam ke5bgca128 fig. 4.6.3(a) restriction example between pipeline operations decode & setup execute0 wait/nop pinout hha execute1 output2 (od) shon/smon clk phase pinout decode & setup execute wait/nop operation request(cpu) operation request(cpu) input operation memhha read srch decode execute0 wait/nop pinout hha execute1 output2 (od) shon/smon pinout operation request(cpu) srch output1 (cpu) shon shon execute0: srch operation execute1: hha output operation from the od bus (1) (2) (3) (a) violation of pipeline operations execute (2) is executed according to hha as the result of execute(1). the wait/nop stage must be in effect for the determination of hha.
4-23 preliminary gigabitcam ke5bgca128 fig. 4.6.3 (b) restriction example between pipeline operations (cont'd) decode & setup execute0 wait/nop pinout hha execute1 output2 (od) shon/smon clk phase pinout decode & setup execute wait/nop operation request(cpu) operation request(cpu) input operation memhha read srch decode & setup execute0 wait/nop pinout hha execute1 output2 (od) shon/smon pinout operation request(cpu) srch output1 (cpu) shon shon execute0: srch operation execute1: hha output operation from the od bus (1) (2) (3) execute (2) is executed according to hha as the result of execute(1). the wait/nop stage must be in effect for the determination of hha. wait/nop wait/nop wait/nop wait/nop wait (b) appropriate pipeline operations
4-24 preliminary gigabitcam ke5bgca128 decode & setup clk phase operation input(cpu) input operation (1) wait/nop wait/nop (c) appropriate pipeline operations execute0: renew the hea operation operation decode execute (2) output1 (cpu) wait/nop wait/nop wait renew the hea operation memhea wait read wait/nop wait/nop execute0 execute0 execute (2) is executed according to hea as the result of execute(1). the wait/nop stage must be in effect for the determination of hea. fig. 4.6.3 (c) restriction example between pipeline operations (cont'd)
4-25 preliminary gigabitcam ke5bgca128 fig. 4.6.4 restrictions between srch operation and search condition definition operation execute clk phase operation request(cpu) input operation register write srch execute0: srch operation execute2: memhha output operation from the od bus execute1: hha output operation from the od bus operation request(cpu) execute0 decode & setup decode & setup wait/nop pinout hha execute1 output2 (od) pinout shon decode & setup execute operation request(cpu) cntl2 write execute2 memhha output2 (od) shon/smon latency:4~7 latency:6~7
4-26 preliminary gigabitcam ke5bgca128 4.7 latency this device operates with the clk signals as the master clock. therefore, there is latency which is characteristic for a synchronous circuit between some action and the following action. latency is counted by the number of rising edge of the clk signals when the phase signal is low from the input operation, as shown in fig. 4.7.1, 4.7.2 for example, fig. 4.7.1 shows that the output latency of the cpu port is 4. fig. 4.7.2 shows that the output latency of the output port is 5. table 4.7.1 shows the output latency. there is also execution latency in read/write operation by commands or registers. (see fig. 4.6.1) the user that the values for latency can be modified by writing to the cntl2 register. fig. 4.7.1 output latency on the cpu port t1: output delay time from clk which is provided in chapter 9 clk phase cen dat<31:0> register value latency = 4 t1 (1) (2) (3) (4) operation input (5) count from this clock oedatn register read
4-27 preliminary gigabitcam ke5bgca128 clk phase cen od<20:0> output latency =5 t1 count from this clock (1) (2) (3) (4) input operation (5) operation oeodn fig. 4.7.2 output latency on the output port t1: output delay time from clk which is provided in chapter 9 table 4.7.1 output latency pins latency dat<31:0> latency is fixed to be 4. latency (oedatn => dat<31:0>) is 1. latency can b e s elected from 4, 5, 6, an d 7 in hha/hea o utp ut. od<20:0> latency from the operation to renew the hea is equal to the hea/hha latency. latency can be selected from 6 and 7 in memhha output. latency (oeodn => od<20:0>) is 1. latency can be selected from 4 and 5. shon latency is 2.5 when th e srst comman d is execu ted. (see fig. 9.4.3) latency is 0.5 fro m the rstn low p uls e. (see fig. 9.4.3) latency is fixed to be 5. smon latency is 2.5 when th e srst comman d is execu ted. (see fig. 9.4.3) latency is 0.5 fro m the rstn low p uls e. (see fig . 9.4.3) flon when mem_heaai is accessed or the gen_fl, nxt_he, str1_heaai, str2_heaai, str1_autai, or str2_autai command is executed, latency is 2.5. latency is 2 when the srst command is executed. latency is 0 from the rstn low pulse. phon when the search operation by the srchn pin or the srch command is executed, latency is 2.5. latency is 0 from the rstn low pulse. pmon when the search operation by the srchn pin or the srch command is executed, latency is 2.5. latency is 0 from the rstn low pulse. when the srst, str_devid, end_devid, and nxt_pr command is executed, latency is 2.
5-1 preliminary gigabitcam ke5bgca128 normal mode devid mode power on device reset str_devid command end_devid command fig 5.3.1.1 device id registration 5. connection 5.1 initialization there are two types of initialization for this device: hard- ware reset by setting the rstn pin to a low level, and soft- ware reset by executing the srst command. hardware reset must be done after the power is on. hardware reset or software reset executes the following ini- tialization: 1) initializes device id *1 2) initializes registers 3) sets empty bits of all entries (all entries are empty) 4) clears permanent bits of all entries 5) clears access bits of all entries 6) phon = 1, shon = 1 7) pmon = 1, smon = 1 8) flon = 1 *1 device id must be registered after reset when devices are cascaded. the gen_fl command must be executed after registration to the cam table. 5.2 single device operation a device reset either by a hardware reset using the rstn low pulse or software reset using the srst command auto- matically sets the device id to 00000 and the ld bit to 1. the ld bit means the last device in a cascaded system. therefore, it is not necessary to set the device id by using the devid mode in the single device operation. the phin and pmin pins must be pulled up and the flin pin must be pulled down with a single device. when used in a single device operation, the device acts as one with hit/empty priority if there is any hit/empty entry in the device. on the other hand, it acts as the last device if there is no hit/empty entry in the device. therefore, the be- havior is the same in the broadcast method as in the device select method, but some commands must be executed in the device select method according to the condition of table 6.2 , and some registers must be accessed in the device select method according to the condition of table 7.4.1, even in this case.
5-2 preliminary gigabitcam ke5bgca128 device id =0 device id =1 device id =2 device id =m 15 (ld) 0 0 0 0 0 0 0 devidl register 0 1 0 0 0 0 0 31 0 0 1 0 0 0 0 31 0 31 m(binary) 1 31 clk phase add<5:0> dat<31:0> cen rwn coml devidl 00000000h 00003000h coml coml devidl str_devid command write to devid register nxt_pr command 00000001h write to devid register 00003000h ..... ..... devidl m coml 00002800h end_devid command devid mode 00000000h nxt_pr command write to devid register 15 (ld) 15 (ld) 15 (ld) fig.5.3.1.2 device id registration procedure
5-3 preliminary gigabitcam ke5bgca128 5.3 cascade connection 5.3.1 device id registration the device can be cascaded to use a maximum of 32 devices. a cascaded system can be treated as one device which has a larger table size. it is necessary to define the device id in the devid register in order to identify each device in the operation of a cascaded system. the procedure for registra- tion of the device id is shown in fig. 5.3.1.2. in order to set the device id, the devices in a cascaded system must be moved into the devid mode by the str_devid command as shown in fig. 5.3.1.1. the str_devid command enables the user to apply read/write operations to the devid register of the highest (top) device in the cascaded system. the device id is set in the di<4:0> of the register. after that, the device id of the next device can be set by the nxt_pr command. the registration should be repeated down the chain until each device is given a unique device id by repeating these operations. if the str_devid command is executed among these opera- tions, it returns to the status where the devid register of the highest (top) device can be read/written. the device id must be a continuous number starting from the top device. the ld in the last device devid register must be set to 1. this bit indicates that the device has the lowest priority, and it is used to control the data outputs. the ld bits of all devices except the last device must be set to 0. after the devid registers of all devices are set, the devices should be moved out of the devid mode and into the nor- mal operation mode by executing the end_devid com- mand. the devices must leave the devid mode after all de- vice ids are set, because operations like table configura- tion or search cannot be executed correctly in the devid mode. waiting time is recommended to ensure that the pmin and pmon pins become stable. the device ids of all devices are initialized to the same value of 00000 after device reset. the operations de- scribed above, from the str_devid command, must be ex- ecuted after device reset. if only one device is used, the device id registration is not necessary. do not register the device id in normal operation mode once the device id is set after device reset. 5.3.2 priority in a cascaded system, the data buses of the cpu port and the output port must be connected to all devices. as for the cpu port, the same data is written to all devices through dat<31:0> and the same pipeline is executed in all devices. the output device is automatically determined in the broad- cast method and the device in which the memhha or the memhea register is written, or the device in which the str_hha, the str_hea, or the str_aut command is executed, is also determined automatically. as for the out- put port, all devices output the search results respectively. the output port must therefore be controlled by the users logic using the shon when there is a multi-hit in the system, when there are many devices with a single hit, or when hea is set to be output in a no hit case. the empty priority is controlled in this device, but the hit priority is not controlled in order to realize a higher speed. the hha as a result of the multi-hit in the device therefore becomes invalid, and the write operation to the entry desig- nated by the hha is not executed. the above-mentioned priority control is, however, executed in the cascaded sys- tem including the device in which the multi-hit occurs. it is also possible not to write, regarding the multi-hit in the sys- tem as illegal status by the cascade connection method de- scribed later.
5-4 preliminary gigabitcam ke5bgca128 ke5bgca128 phin pmin phon pmon flin flon cen rwn clk srchn phase ke5bgca128 phin pmin phon pmon flin flon cen rwn clk srchn phase ke5bgca128 phin pmin phon pmon flin flon cen rwn clk srchn phase multi hit sin g le hit single hit phon= l phon= h phon= l pmon= l pmon= l pmon= l flon=l flon=h flon=h no sin g le hit priorit y no em p t y priorit y sin g le hit priorit y em p t y priorit y no sin g le hit priorit y no em p t y priorit y no empty entry empty entry no empty entry no write no write data is written the hha address fig.5.3.2.1 cascade connection
5-5 preliminary gigabitcam ke5bgca128 three priorities are used for these controls: the single-hit priority, the empty priority, and the devid priority. the phin, pmin, flin, phon, pmon, and flon pins are used to propagate the priorities. (1) single hit priority in a cascaded system, the uppermost located device among all devices that have hit entries, except the devices in which the multi-hit occurs, is defined as having hit priority. (see fig. 5.3.2.1) this priority is propagated through the phon and the phin. when a multi-hit does not occur in a device and the upper devices have single hit priority, the phon of the device outputs 0. when neither single hit nor multi-hit occurs in the device and the upper devices do not have single hit priority, the phon of the device outputs 1. in order to have a device having single hit priority, the phin of the device must be set to 1. (2) empty priority in a cascaded system, the uppermost located device among all devices that have empty entries is defined as having empty priority (see fig.5.3.2.1). this priority is propagated through the flon and the flin. when a device is full sta- tus and the upper devices are full, the flon of the device outputs 0. when the device is not full or the upper de- vices are not full, the flon of the device outputs 1. in order to have a device having empty priority, the flin of the device must be set to 0. (3) devid priority devid priority specifies which device accepts the device id data in the devid mode. devid priority is propagated through the pmin and pmon pins in the devid mode. however, the pmin and pmon pins propagate multi-hit in- formation in something other than the devid mode. (4) last device the device located at the bottom of the cascaded chain must be known in order to perform internal control of the device. the ld bit in the devid register of the bottom de- vice must be set to 1 to indicate that it is the last de- vice. for example, the last device stores the total hit and empty information of the cascaded system in the hha and hea registers. the last device outputs the bits: hv, ev, syh, sym, sye, ht, mh, the address with hit priority or empty priority when the hha or hea register is read in the broad- cast method. if there is no device having single hit priority, the last device outputs the data of the hha register in the broadcast method. the hv flag of the output data is 1 and that indicates that the hha is invalid. in the same manner, if there is no device having empty priority, the last device outputs the data of the hea register in the broadcast method. the ev flag of the output data is 1 and that indi- cates that the hea is invalid. in a cascade system, for regis- ters that have the same data in each device, such as the cntl1/2 and the sconf register, when these registers are read in the broadcast method, the last device outputs the registers data. 5.3.3 cpu port in a cascaded system read/write registers read/write operations (including command execution) can be performed by both the broadcast and the device select method. this selection is defined in the devsel register. the br bit in the devsel register must be set to 0 in the device select method the selected device can be specified by the ds<4:0> in the devsel register. the br must be set to 1
5-6 preliminary gigabitcam ke5bgca128 in the broadcast method. when data is written to a register, one of the following operations is executed according to the attribute of the register: (1) write to all devices simultaneously (2) write to the device which has single hit priority (3) write to the device which has empty priority when data is read from a register, one of the following op- erations is executed according to the attribute of the regis- ter: (1) read from the last device (2) read from the device which has single hit priority (3) read from the device which has empty priority for registers which must have common data for all devices, the device select method is invalid and data is written to appropriate register of all the devices. some registers must be accessed by the device select method. see table 7.4.1 in chapter 7 for read/write availability of each register in the broadcast method/device select method and the output de- vice that is accessed in the broadcast method. command execution the command of the device should be executed by the broadcast method in a cascaded system. the device to which the command execution applies is automatically de- cided internally in this case. cascade connection of the cpu port cascade connection methods of multiple devices are shown below: (1) priority control without the external logic (2) priority control with the external logic a cascade connection can be realized by either of the two methods. table 5.3.3.1 shows the relationship between cas- cade input pins and their actions. when the priority is con- trolled by the external logic, the external circuit must be de- signed referring to table 5.3.3.1 and fig. 5.3.3.3. (1) connection without the external logic in this method, the external logic is not necessary to control the priority (see fig. 5.3.3.1). however, additional propaga- tion time is needed according to the number of cascaded devices. this is because the priority signal is cascaded through each of the devices. we define two types of multi- hits: when there are multiple hits within a single device, or when there are two devices in a cascaded system that have a single hit. when two devices have a single multi-hit, the data is written in the hha address of the uppermost single hit priority device in the cascaded system. for devices that have multiple hits within a single device, data will not be written to the hha address. data will be written to the hha address in the next device in the cascade chain that has a single hit priority. (see fig. 5.3.2.1) the commands str1_aut, str2_aut, str1_autai, and str2_autai cannot be executed in this connection method. ac characteristics in this method this device can automatically perform its internal control function by using respective priority signals. after the pri- ority is changed by some action, the next operation which needs priority determination must wait a certain time accord- ing to the number of cascaded devices. as shown in fig. 5.3.3.2, the total time between some action and the next op- eration which needs priority determination is required for priority determination. t1: latency of the action in the top device t2: delay time after latency of the action in the top device
5-7 preliminary gigabitcam ke5bgca128 t3: propagation delay of priority signal from the top device to the last device t4: setup time for the action which needs priority determina- tion in the last device (2) connection with the external logic in this method, external priority control logic is used to mini- mize the cascade delay of the system (see fig. 5.3.3.3). the external control logic must generate the priority signal of each device, phin. this is determined from the shon pin, which is output by each device in hit priority control. in the case of writing to the mem_hha register or writing by the str1_hha or the str2_hha command, the phin signal is made with consideration of the writing timing in the device as shown in fig. 5.3.3.4. when the str1_aut or the str2_aut command is used in a cascaded system, the phin of each device must be controlled with consideration of the action timing in each device as shown in fig. 5.3.3.4. ac characteristics in this method this device can automatically perform its internal control function by using respective priority signals. after the pri- ority is changed by some action, the next operation which needs priority determination must wait a certain time accord- ing to the number of cascaded devices. as shown in fig. 5.3.3.4, the total time between some action and the next op- eration which needs priority determination is required for priority determination. t1: latency of the action in each device t2: delay time after latency of the action in each device t3: propagation delay of priority signal from the external pri- ority control circuit to each device t4: setup time for the action which needs priority determina- tion in each device
5-8 preliminary gigabitcam ke5bgca128 table 5.3.3.1 operation by hit priority(in the broadcast method) operation by hit p riority (in the broadcast method) device external pin*1 op eration that needs status in device op eration pm in phin flin p riority determination x 0 x m em hha, single hit no operation x 0 x m em hha_at(write) no hit no operation x 0 x no hit no operation x 0 x m em hha, single hit hi-z outp ut x 0 x m em hha_at(read) m ulti-hit hi-z outp ut x 0 x no hit hi-z outp ut x 0 x hha(read) single hit hi-z outp ut x 0 x dat<30,27,26,24>,<23:0> m ulti-hit hi-z outp ut x 0 x *2 no hit hi-z outp ut v *3 0 x hha(read) single hit hi-z outp ut or if the last device, outp ut v *3 0 x dat<31,29,28,25> m ulti-hit hi-z outp ut or if the last device, outp ut v *3 0x*3 no hit hi-z outp ut or if the last device, outp ut x 0 x str1_hha, str2_hha single hit no operation x 0 x m ulti-hit no operation x 0 x no hit no operation x 0 x str1_aut, str2_aut single hit no operation x 0 x m ulti-hit no operation x 0 x no hit no operation *1 "x" means "don't care." *2 each device drives dat<30,27,26,24>,<23:0> in the 32-bit cpu bus since this is respective information of each device. *3 the last device drives dat<31,29,28,25> in the 32-bit cpu bus since this is information of the cascaded sy stem. flin of the last device must be determined for the sye flag to be output exactly in dat<25>. pm in of the last device must be determined for the sym flag to be output exactly in dat<28>.
5-9 preliminary gigabitcam ke5bgca128 table 5.3.3.1(cont'd) device external pin*1 op eration status in device op eration pm in phin flin x 1 x m em hha, single hit write x 1 x m em hha_at(write) m ulti-hit no operation x 1 x no hit no operation x1x memhha, m em hha_at(read) single hit outp ut x1x m ulti-hit hi-z outp ut or if the last device, outp ut invalid data x1x no hit hi-z outp ut or if the last device, outp ut invalid data x 1 x hha(read) single hit outp ut x 1 x bit<30,27,26,24>,<23:0> m ulti-hit hi-z outp ut or if the last device, outp ut invalid address x1x*4 no hit hi-z outp ut or if the last device, outp ut invalid address v *5 1 x hha(read) single hit hi-z outp ut or if the last device, outp ut valid address v *5 1 x bit<31,29,28,25> m ulti-hit hi-z outp ut or if the last device, outp ut valid address v *5 1x*5 no hit hi-z outp ut or if the last device, outp ut valid address x 1 x str1_hha, str2_hha, single hit*6 write to hha*6 x 1 x m ulti-hit*6 no operation x 1 x no hit*6 no operation x 1 x str1_aut, str2_aut, single hit*7 write to hha x 1 x str1_autai, or ,str2_autai m ulti-hit*7 no operation x10 no hit with emp ty ent ry *7 write to hea*8 x10 no hit without emp ty ent ry *7 no operation x11 no hit with emp ty ent ry *7 no operation x11 no hit without emp ty ent ry *7 no operation *4 each device drives dat<30,27,26,24>,<23:0> in the 32-bit cpu bus since this is respective information of each device. *5 the last device drives dat<31,29,28,25> in the 32-bit cpu bus since this is information of the cascaded sy stem. flin of the last device must be determined for the sye flag to be output exactly in dat<25>. pm in of the last device must be determined for the sym flag to be output exactly in dat<28>. *6 str*_hha is str1_hha or str2_hha . if the search result by the cm p1 register is a single hit, the str1_hha command executes the write op eration that the data in the cm p1 register is written in the entry indicated by hha1. if the search result by the cm p2 register is a single hit, the str2_hha command executes the write op eration that the data in the cm p2 register is written in the entry indicated by hha2. *7 str*_aut is str1_aut or str2_aut. if the search result by the cm p1 register is a single hit, the str1_aut command executes the write operation that the data in the cm p1 register is written in the entry indicated by hha1. if there is no hit, write in the entry indicated by hea1. if the search result by the cm p2 register is a single hit, the str2_aut command executes the write op eration that the data in the cm p2 register is written in the entry indicated by hha2. if there is no hit, write in the entry indicated by hea2. *8 if str*_autai is executed, renewal of the hea address is performed simultaneously .
5-10 preliminary gigabitcam ke5bgca128 table 5.3.3.1(cont'd) op eration by empty p riority (in the broadcast method) device external pin*1 op eration status in device op eration pm in phin flin xx0 memhea, m em hea_at(write) with emp ty entry write*11 x x 0 or m em heaai without emp ty entry no operation xx0 memhea, m em hea_at(read) with emp ty entry outp ut*11 x x 0 or m em heaai without emp ty entry hi-z outp ut or if the last device, outp ut invalid data x x 0 hea(read) with emp ty entry outp ut x x 0 bit<30,27,26,24>,<23:0>*9 without emp ty entry hi-z outp ut or if the last device, outp ut invalid address v *10 v *10 0 hea(read) with emp ty entry hi-z outp ut or if the last device, outp ut valid address v *10 v *10 0 bit<31,29,28,25>*10 without emp ty entry hi-z outp ut or if the last device, outp ut valid address x x 0 str1_hea, str2_hea, with emp ty entry write*12 x x 0 str1_heaai, or str2_heaai without emp ty entry no operation x x1 memhea, m em hea_at(write) wit h emp t y ent ry no operation x x 1 or m em heaai without emp ty entry no operation xx1 memhea, m em hea_at(read) with emp ty entry hi-z x x 1 or m em heaai without emp ty entry hi-z x x 1 hea(read) with emp ty entry hi-z x x 1 bit<30,27,26,24>,<23:0> without emp ty entry hi-z x x 1 hea(read) with emp ty entry hi-z outp ut or if the last device, outp ut valid address x x 1 bit<31,29,28,25> without emp ty entry hi-z outp ut or if the last device, outp ut valid address x x 1 str1_hea, str2_hea, with emp ty entry no operation x x 1 str1_heaai, or str2_heaai without emp ty entry no operation *9 each device drives dat<30,27,26,24>,<23:0> in the 32-bit cpu bus since this is respective information of each device. *10 the last device drives dat<31,29,28,25> in the 32-bit cpu bus since this is information of the cascaded system. pm in of the last device must be determined for the sym flag to be output exactly in dat<28>. phin of the last device must be determined for the syh flag to be output exactly in dat<29>. *11 if the m em heaai register is accessed, renewal of the hea address is p erformed simultaneously. *12 if the str1_heaai or the str2_heaai command is executed, renewal of the hea address is performed simultaneously.
5-11 preliminary gigabitcam ke5bgca128 table 5.3.3.1(cont'd) op eration by hit priority (in the device select method). in devices that are not selected, no operation is performed for write group op eration, and hi-z outp ut is performed for read group op eration. device external pin*1 op eration status in device op eration pm in phin flin x x x m em hha, single hit write x x x m em hha_at(write) m ulti-hit no operation x x x no hit no operation x x x m em hha, single hit outp ut x x x m em hha_at(read) m ulti-hit outp ut invalid data x x x no hit outp ut invalid data x x x hha(read) single hit outp ut x x x bit<30,27,26,24>,<23:0>*13 m ulti-hit outp ut invalid address x x x no hit outp ut invalid address x x x hha(read) single hit outp ut x x x bit<31,29,28,25>*14 m ulti-hit outp ut x x x no hit outp ut x x x str1_hha or str2_hha single hit*15 write x x x m ulti-hit*15 no operation x x x no hit*15 no operation x x x str1_aut, str2_aut, single hit*16 write to hha*16 x x x str1_autai, or ,str2_autai m ulti-hit*16 no operation x x x no hit*16 write to hea*16,17 *13 each device drives dat<30,27,26,24>,<23:0> in the 32-bit cpu bus since this is respective information of each device. *14 the last device drives dat<31,29,28,25> in the 32-bit cpu bus since this is information of the cascaded sy stem. *15 str*_hha is str1_hha or str2_hha. if the search result by cm p1 is a single hit, the str1_hha command executes the write op eration that the data in the cm p1 register is written in the entry indicated by hha1. if the search result by cm p2 is a single hit, the str2_hha command executes the write operation that the data in the cm p2 register is written in the entry indicated by hha2. *16 str*_aut is str1_aut or str2_aut. if the search result by cm p1 is a single hit, the str1_aut command executes the write op eration that the data in the cm p1 register is written in the entry indicated by hha1. if there is no hit, write in the entry indicated by hea1. if the search result by cm p2 is a single hit, the str2_aut command executes the write op eration that the data in the cm p2 register is written in the entry indicated by hha2. if there is no hit, write in the entry indicated by hea2. *17 if the str1_autai or the str2_autai command is executed, renewal of the hea address is p erformed simultaneously .
5-12 preliminary gigabitcam ke5bgca128 table 5.3.3.1(cont'd) op eration by empty p riority (in the device select method) in devices that are not selected, no operation is performed for write group op eration, and hi-z outp ut is performed for read group operation. device external pin*1 op eration status in device op eration pm in phin flin x x x m em hea(write) wit h emp t y ent ry write*20 x x x or m em hea_at without emp ty entry no operation x x x memhea, wit h emp t y ent ry outp ut*20 x x x or m em heaai_at(read) without emp ty entry outp ut invalid data x x x hea(read) wit h emp t y ent ry outp ut x x x bit<30,27,26,24>,<23:0>*18 without emp ty entry outp ut invalid address x x x hea(read) wit h emp t y ent ry outp ut x x x bit<31,29,28,25>*19 without emp ty entry outp ut x x x str1_hea, str2_hea wit h emp t y ent ry write*21 x x x or str1_heaai, str2_heaai without emp ty entry no operation *18 each device drives dat<30,27,26,24>,<23:0> in the 32-bit cpu bus since this is respective information of each device. *19 the last device drives dat<31,29,28,25> in the 32-bit cpu bus since this is information of the cascaded system. *20 if the m em heaai register is accessed, renewal of the hea address is p erformed simultaneously. *21 if the str1_heaai or the str2_heaai command is executed, renewal of the hea address is p erformed simultaneously.
5-13 preliminary gigabitcam ke5bgca128 fig. 5.3.3.1 simple cascade connection ke5bgca128 phin pmin phon pmon flin flon cen rwn clk srchn phase ke5bgca128 phin pmin phon pmon flin flon cen rwn clk srchn phase ke5bgca128 phin pmin phon pmon flin flon cen rwn clk srchn phase
5-14 preliminary gigabitcam ke5bgca128 operation1 clk phase cen t1 + t2 *1 valid operation2 valid t3 t4 3 clocks *2 valid 5 clocks *3 t3 t4 o p eration which chan g es p riorit y operation which needs priority determination phin, pmin, flin of the last device phin, pmin, flin of the last device start command or re g ister access phon, pmon, flon of the top device si g nal p ro p a g ation fig. 5.3.3.2 priority decision timing in a cascaded system (simple cascade connection) *1 ? when the operation which changes the priority falls under one of the cases shown below, t1 is latency 1.5 (= 3 clock). 1) search by the srchn pin 2) search by the srch command 3) execution of the memheaai(read/write), nxt_hea, gen_fl, or str1_heaai/ str2_heaai command ? when the operation which changes the priority falls under reset by the srst command, t1 is latency 1 (= 2 clock). ? when the operation which changes the priority falls under reset by the rstn pulse, t1 is latency 0 (= 0 clock). t2 is the same in any case shown above. *2 if the operation which needs priority determination falls under one of the cases shown below, the setup time is counted from 3 clock after input of the operation. 1) execution of the memhha(read/write), memhea(read/write), memheaai(read/ write), str1_hha/str2_hha, str1_hea/ str2_hea, or str1_heaai/str2_heaai command *3 if the operation which needs priority determination is hha(read) or hea(read), the setup time is counted from 5 clock after input of the operation.
5-15 preliminary gigabitcam ke5bgca128 to external priority control logic from external logic from external logic external priorit y control lo g ic shon0 shonn flon0 flonn phin0 phinn flin2 flinn from external logic clk to external priority control logic to external priority control logic phase pmin2 pminn pmon0 pmonn *1 phin and pmon are used to propagate device priority and multi-hit flag. ke5bgca128 phin pmin phon pmon flin flon shon smon oeodn cen rwn clk srchn phase ke5bgca128 phin pmin phon pmon flin flon shon smon oeodn cen rwn clk srchn phase ke5bgca128 phin pmin phon pmon flin flon shon smon oeodn cen rwn clk srchn phase fig.5.3.3.3 cascaded system with external priority control logic example
5-16 preliminary gigabitcam ke5bgca128 operation1 clk phase cen t1 + t2 *1 valid operation2 valid t3 t4 3 clocks *2 valid 5 clocks *3 t3 t4 valid t5 + t6 *4 start command or re g ister access o p eration which chan g es the p riorit y operation which needs priority determination phin, pmin, flin of each device phin, pmin, flin of each device signal propagation phon, pmon, flon of each device shon (latency=4) of each device *1 ? when the operation which changes the priority falls under one of the cases shown below, t1 is latency 1.5 (= 3 clock). 1) search by the srchn pin 2) search by the srch command 3) execution of the memheaai(read/write), nxt_hea, gen_fl, str1_heaai/ str2_heaai, or str1_autai / str2_autai command ? when the operation which changes the priority falls under reset by the srst command, t1 is latency 1 (= 2 clock). ? when the operation which changes the priority falls under reset by the rstn pulse, t1 is latency 0 (= 0 clock). t2 is the same in any case shown above. *2 if the operation which needs priority determination falls under one of the cases shown below, the setup time is counted from 3 clock after input of the operation. 1) execution of the memhha(read/write), memhea(read/write), memheaai(read/ write), str1_hha/str2_hha, str1_hea/ str2_hea, str1_heaai/str2_heaai, str1_aut/str2_aut, or str1_autai/ str2_autai *3 if the operation which needs priority determination is hha(read) or hea(read), the setup time is counted from 5 clock after input of the operation. *4 in fig. 5.3.3.4, the latency of the shon of each device is 4. therefore, t5 is latency 4 (= 8 clock) and t6 is delay time. fig.5.3.3.4 priority decision timing in a cascaded system with external priority control logic
5-17 preliminary gigabitcam ke5bgca128 table 5.3.3.2 relations between the operation which changes the priority and the operation which needs priority determination *1 output variations of phon, pmon, shon, and smon are shown below. phon output phin pmin status in the device low 0 don't care single hit only low 0 don't care multi-hit low 0 don't care others low 1 don't care single hit only high 1 don't care multi-hit high 1 don't care others operation1 operation2 operation which changes the priority operation which needs priority determination single hit the priority propagation pins whose status changes comman d pins to consider search by the srchn pin phon, pmon, memhha(read/write) phin command shon, smon *1 memhha_at(read/write) phin search by the srch command phon, pmon, hha(read) phin command shon, smon *1 str1_hha command phin reset by the srst command phon, pmon, str2_hha command phin command shon, smon *1 str1_ aut comman d str2_aut command phin, pfin reset by the rstn pulse phon, pmon, shon, smon *1 str1_autai command str2_autai command phin, pfin empty priority propagation pins whose status changes comman d pins to consider memheaai(read/write) pfon memhea(read/write) flin command command memhea_at(read/write) flin nxt_hea command flon *2 memhaeaai(read/write) flin gen_fl command hea(read) flin str1_heaai command str2_heaai command flon * 2 str1_ hea co mmand str2_hea command flin str1_autai command (in no hit) str2_autai command (in no hit) flon * 2 str1_ heaai co mmand str2_heaai command flin reset by the srst command flon *2 str1_aut command str2_aut command phin, flin reset by the rstn pulse flon *2 str1_autai command str2_autai command phin, flin
5-18 preliminary gigabitcam ke5bgca128 pmon output phin pmin status in the device low 0 0 single hit only low 0 0 mu lti-hit low 0 0 others low 01 single hit only low 0 1 mu lti-hit high 0 1 others low 1 0 single hit only low 1 0 mu lti-hit low 1 0 others high 1 1 single hit only low 1 1 mu lti-hit high 1 1 others shon output phin status in the device low don't care single hit only high don't care others smon output phin status in the device low don't care multi-hit high don't care others table 5.3.3.2 relations between the operation which changes the priority and the operation which needs priority determination (cont'd) *1 output variations of phon, pmon, shon, and smon (contd) *2 output variations of flon flon output flin status in the device high 0 empty entry in the device low 0 no empty entry in the device high 1 empty entry in the device high 1 no empty entry in the device
5-19 preliminary gigabitcam ke5bgca128 str_aut command in a cascaded system the str_aut command executes the str_hha action when there is a hit in the device and the str_hea action when there is no hit in the device as mentioned before. after the search operation, each device is going to execute either the str_hha or the str_hea action referring to its own search result. therefore, in a cascaded system, the phin must be controlled by determining the priority with hit infor- mation in the system before the str_aut command is ex- ecuted in devices. (see fig. 5.3.3.4) the phin of each device should be created from the shon signal of the each device by the external logic. operation in hit (same as str_hha) when there is a hit in the device, the data in the cmp regis- ter is going to be written in the entry indicated by the hha register. unless there is a multi-hit in the device, the str1_aut uses the hha1 which is a search result of the cmp1, and the str2_aut uses the hha2 which is a search result of the cmp2. this operation is not performed when there is not single hit priority (phin = "0"). operation in no hit this operation is a little bit different from the normal opera- tion of the str_hea command. the str_hea command takes only the empty priority into account in a cascaded system. the str_hea command is going to be executed in the device where there are no hits even though there is a hit in other devices, because the hit information in the device alone is taken into account in the str_hea operation by the str_aut command. therefore, when there is a hit in some other devices, the str_hea operation must be re- strained in the device where there are no hits according to the timing shown in fig. 5.3.3.4. the phin signal is as the control signal to perform this function in the device. only when the phin is 1, is the str_hea operation performed in the no hit case of the str_aut command. therefore, when the str_aut command is used in a cascaded sys- tem, the phin signal must be controlled by external logic, while taking this into account. when there are no hits in all devices in the system, the str_hea operation is performed in the device that has the highest empty priority. table 5.3.3.2 shows the operation that changes the priority and the operation that needs priority determination.
5-20 preliminary gigabitcam ke5bgca128 5.3.4 output port in a cascaded system table 5.3.4.1 shows the output conditions of the output port and fig. 5.3.4.1 (a/b) shows the timing. if there is no multi-hit in the system, if there are many devices with a single hit, and if the hea output is not required, the output control is performed in each device and can be realized with- out any external logic by connecting the output ports of the respective devices. in this case, hha/hea latency = 4 can be selected. when there is multi-hit in the device, invalid hha is output in the od port as same as hha/hea latency = 5, 6, 7. however, in case of hha/hea latency = 4, invalid flag (od<15>) does not indicates whether outputting hha is valid or not. the smon signal (latency =5) indicates whether the output hha is valid or not. (see fig. 5.3.4.2 (a)) if there is a multi-hit in the system or the hea output is required, collisions on the output port happen. in this case, the oeodn control from the shon signal by the external logic is necessary. (see fig. 5.3.4.2 (b)) timing in a cascaded system fig. 5.3.4.3 shows the timing by the external control logic in a cascaded system. the oeodn signal must be controlled by the external logic. the latency of oeodn is 1. t1: latency of shon (latency is 4 in fig. 5.3.4.3) t2: delay time of the shon signal t3: latency of flon (latency is 1.5 = 3 clock.) t4: delay time of the flon signal t5: output latency of the od port (hha latency is 5 in fig. 5.3.4.1 (a/b)) t6: delay time of the od port signal t7: setup time of the oeodn signal t8: delay time of the signal from the external control logic
5-21 preliminary gigabitcam ke5bgca128 table 5.3.4.1 output conditions of the output port opsl: od<20:0> output is selected by opsl input. hit/mis-hit: it indicates whether the search result is hit or not. mhn: it indicates whether the search result is multi-hit or not. hea output: the sconf register indicates whether hea output is necessary or not when there are no hits. (0: no output, 1: output) flon: it indicates whether cam table is full or not. opsl hit /mis-hit mhn heaoutput flon od output *1 100xxhha(invalid)(*2) 101xx hha(*3) hha s tate 1 1 1 0 x hi-z 111 1 0hea(invalid)(*4) 111 1 1 hea(*5) 000xx invalid 0 0 1 x x memhha memhha state 0 1 1 0 x hi-z 011 1 0 hi-z 011 1 1 hi-z bit15 of the od port (od<15>) is valid flag which indicates status of the outputting hha/hea. 0:valid , 1:in valid bit14 of the od port (od<14>) is hha/hea flag which indicates whether output of the od port is hha or hea. 0:hha ou tpu t 1:hea o utp ut (*1) even if opsl is set to "1" after the memhha output is determined (if latency is 6, after then), hha or hea is output in the right way. if opsl is set to "0" before the memhha output is determined (if the latency is 6,before then), the memhha searched before is output. refer to fig . 5.3.4.2. (*2) od<20:16>: devid is o utp ut. (*4) od<20:16>: devid is o utp ut. od<15> :1 (inv alid) od<15> :1 (inv alid) (in cas e of hha/hea latency = 5, 6, 7) (in cas e of hha/hea latency = 5, 6, 7) od<15> :x (unknown) (in case of hha/hea latency = 4) od<15> :x (unknown) (in case of hha/hea latency = 4) od<14> :0 (hha) od<14> :1 (hea) od<13:11>: u nkn own od<13:11>: u nkn own od<10:0> : hha od<10:0> : hea (*3) od<20:16>: devid is o utp ut. (*5) od<20:16>: devid is o utp ut. od<15> :0 (v alid) od<15> :0 (v alid) (in cas e of hha/hea latency = 5, 6, 7) (in cas e of hha/hea latency = 5, 6, 7) od<15> :x (unknown) (in case of hha/hea latency = 4) od<15> :x (unknown) (in case of hha/hea latency = 4) od<14> :0 (hha) od<14> :1 (hea) od<13:11>: u nkn own od<13:11>: u nkn own od<10:0> : hha od<10:0> : hea
5-22 preliminary gigabitcam ke5bgca128 clk phase cen srch operation od<20:0> memhha latency =6 (memhha) (1) (2) (3) (4) hha/hea hha/hea latency =5 (hha) (5) (6) latency opsl clk phase cen srch operation od<20:0> memhha latency =6 (memhha) (1) (2) (3) (4) hha/hea latency =5 (hha) (5) (6) latency opsl memhha count from this clock operation input o utput the same hha/hea count from this clock operation input when the latency of hha is 5 and that of memhha is 6 when the latency of hha is 5 and that of memhha is 6 memhha last searched fig. 5.3.4.1(b) timing of the output condition fig. 5.3.4.1(a) timing of the output condition
5-23 preliminary gigabitcam ke5bgca128 ke5bgca128 shon oeodn flon od<20:0> cen rwn clk srchn phase ke5bgca128 shon oeodn flon od<20:0> cen rwn clk srchn phase ke5bgca128 shon oeodn flon od<20:0> cen rwn clk srchn phase fig.5.3.4.2 (a) simple cascade connection example
5-24 preliminary gigabitcam ke5bgca128 to external priority control lo g ic external priority control logic shon0 shonn flon0 flonn to external priority control logic to external priority control logic oeodn0 oeodnn from external priority control logic from external priority control logic from external priority control lo g ic ke5bgca128 shon oeodn flon cen rwn clk srchn od<20:0> phase ke5bgca128 shon oeodn flon cen rwn clk srchn od<20:0> phase ke5bgca128 shon oeodn flon cen rwn clk srchn od<20:0> phase fig.5.3.4.2 (b) cascade connection example (signals of the output port)
5-25 preliminary gigabitcam ke5bgca128 operation clk phase cen valid t1 + t2 *1 hha/hea output oeodn opsl t5 t6 t7 od<20:0> valid t3 + t4 *2 t8 start command or register access shon(latency=4) of each device flon of each device fig. 5.3.4.3 timing design in a cascaded system
6-1 preliminary gigabitcam ke5bgca128 6. command descriptions 6.1 command functions table 6.1 command table all commands are executed by writing the 16-bit op-code into the coml register. table 6.1 shows the command names, operation codes, functions and descriptions. command command cycle function description group name (op-code) no. reset srst 2 software executes device reset. the function of this command is the (0000h) res et s ame as a low p uls e inp ut to the rstn p in . all entries (including entries whose permanent bit is set) become empty (inactive) by this command. the flag pins are set as follows: phon = high, pmon = high, flon = high shon = high, smon = high c onfiguratio n str_devid 1 devid mode start switches the device to the devid mode in order to define (2000h) th e device id. end_devid 1 devid mode end ends the devid mode. (2800h) nxt_pr 1 shift devid shifts the devid priority to the next device in the devid (3000h) priority mod e. cam table srch1 *1 1 search searches with data in the cmp1 register. (4000h) srch2 *1 1 search searches with data in the cmp2 register. (4200h) prg_al *2 1 purge all entries become empty (inactive) by this command. (6000h) however, an en try wh os e permanen t bit is s et to "1" do es not become empty by this command. prg_ac *2 1 purge all entries whose access bit is set to "1" become empty (6040h) (inactive) by th is comman d. however, an en try wh os e permanent bit is set to "1" does not become empty by this command. prg_nac *2 1 purge all entries whose access bit is not set to "1" become (6080h) empty (inactive) by th is comman d. however, an en try wh os e permanent bit is set to "1" does not become empty by this command.
6-2 preliminary gigabitcam ke5bgca128 command command cycle function description group name (op-code) no. cam table rst_ac 1 reset all clears access bits of all entries. (a000h) a ccess bits rst_pm 1 reset all clears permanent bits of all entries. (a010h) perman ent bits gen_fl 2 confirm the confirms the empty state of the cam table. (8004h) hea regis ter makes the hea reg is ter s tore the entry ad dres s with the highest empty priority. the content of the hea register and the status of the flon pin are also changed. nxt_he 2 renew the hea makes the hea register store an entry address with the next (8008h) reg is ter empty p rio rity . the con tent of the hea reg is ter and th e status of the flon pin are also changed. move str1_ar *1 1 store moves data in the cmp1 register into the entry indicated (c000h) b y the ar reg is ter. str1_hha *1 1 store moves data in the cmp1 register into the entry indicated (c001h) b y the hha reg is ter according to the search result of the cmp1 register write or the srch1 command. str1_hea *1 1 store moves data in the cmp1 register into the entry indicated (c002h) b y the hea reg is ter. str1_heaai*1 2 store moves data in the cmp1 register into the entry indicated (c00ah) by the hea register. renews the hea register simultaneously. str1_aut*1 1 store moves data in the cmp1 register into the entry indicated (c003h) b y the hha reg is ter according to the cmp1 register write or the srch1 command if the search result is a hit. moves data in the cmp1 register into the entry indicated by the hea register if the search result is no hit. moves data in the cmp1 register into the entry indicated by the hha register according to the cmp1 register write str1_autai*1 2 store or the srch1 command if the search result is a hit. moves (c00bh) data in the cmp1 register into the entry indicated by the hea register if the search result is no hit. renews the hea register simultaneously. table 6.1 command table (cont'd)
6-3 preliminary gigabitcam ke5bgca128 *1 mask operation by each bit can be executed by the mask registers (mask0 ~ mask11). these mask registers can be selected by the ms<3:0> pins or the cntl1 register. *2 after the purge (prg_*) command is executed, the status of the access bit of each word is kept. execute the rst_ac command in order to clear all access bits. table 6.1 command table (cont'd) command command cycle function description group name (op-code) no. str2_ar *1 1 store moves data in the cmp2 register into the entry indicated (c200h) b y the ar reg is ter. str2_hha *1 1 store moves data in the cmp2 register into the entry indicated (c201h) b y the hha reg is ter according to the search result of the cmp2 register write or the srch2 command. move str2_hea *1 1 store moves data in the cmp2 register into the entry indicated (c202h) b y the hea reg is ter. str2_heaai*1 2 store moves data in the cmp2 register into the entry indicated (c20ah) by the hea register. renews the hea register simultaneously. str2_aut*1 1 store moves data in the cmp2 register into the entry indicated (c203h) b y the hha reg is ter according to the cmp2 register write or the srch2 command if the search result is a hit. moves data in the cmp2 register into the entry indicated by the hea register if the search result is no hit. str2_autai*1 2 store moves data in the cmp2 register into the entry indicated (c20bh) by the hha register according to the cmp2 register write or the srch2 command if the search result is a hit. moves data in the cmp2 register into the entry indicated by the hea register if the search result is no hit. renews the hea register simultaneously. other nop 1 no operation executes no operation. (e000h)
6-4 preliminary gigabitcam ke5bgca128 6.2 command format the op-code field :op<15:0> is made up of the following fields. ope (3bits): op<15:13> this field defines the type of operation assigned as below. 0h : reset operation 1h : device configuration 2h : search operation 3h : purge operation 4h : empty priority operation 5h : attribute bit operation 6h : store operation 7h : undefined (no operation) conf (2bits): op<12:11> this field defines the type of command in device configura- tion. 0h : str_devid command 1h : end_devid command 2h : nxt_pr command 3h : undefined cmp (2bits): op<10:9> this field defines the selection of the comparand registers. 0h : cmp1 selects 2h : cmp2 selects 3h : undefined 4h : undefined prg (3bits): op<8:6> this field defines the type of purge. 0h : prg_al command 1h : prg_ac command 2h : prg_nac command 3h : undefined 4h : undefined 5h : undefined 6h : undefined 7h : undefined rst (2bits): op<5:4> this field defines the attribute bit to be reset. 0h : access bit 1h : permanent bit 2h : undefined 3h : undefined gen (2bits): op<3:2> this field defines the hea operation method. 0h : no operation 1h : gen_fl operation (determines hea) 2h : nxt_he operation (renews hea) 3h : undefined ar/hha/hea (2bits): op<1:0> this field defines the destination address of the store command. 0h : ar 1h : hha 2h : hea 3h : str_aut command
6-5 preliminary gigabitcam ke5bgca128 table 6.2 command format and conditions for execution notes; : executable : executable (device not selectable. see annotations) x : don't care ope config cmp prg rst gen ar device select op-code (16 bits ) /hha method (3bits) mode sel mode mode /hea msb lsb group 3bits 2bits 2bits 3bits 2bits 2bits 2bits broadcast devsel srst 0 x x x x x x *10000000000000000 str_devid 1 0 x x x x x *10010000000000000 end_devid 1 1 x x x x x *10010100000000000 nxt_pr 1 2 x x x x x *10011000000000000 srch1 2 x 0 x x x x 0100000000000000 srch2 2 x 1 x x x x 0100001000000000 prg_al 3 x x 0 x x x 0110000000000000 prg_ac 3 x x 1 x x x 0110000001000000 prg_nac 3 x x 2 x x x 0110000010000000 gen_fl 4 xxxx1x 1000000000000100 nxt_he 4 xxxx2x *2 *31000000000001000 rst_ac 5 x x x 0 x x 1010000000000000 rst_pm 5 x x x 1 x x 1010000000010000 str1_ar 6 x 0 x x x 0 *4 1100000000000000 str1_hha 6 x 0 x x x 1 *5 *61100000000000001 str1_hea 6 x 0 x x 0 2 *2 *31100000000000010 str1_heaai 6 x 0 x x 2 2 *2 *31100000000001010 str1_aut *7 6 x 0 x x 0 3 *2 *31100000000000011 str1_autai *7 6 x 0 x x 2 3 *2 *31100000000001011 str2_ar 6 x 1 x x x 0 *4 1100001000000000 str2_hha 6 x 1 x x x 1 *5 *61100001000000001 str2_hea 6 x 1 x x 0 2 *2 *31100001000000010 str2_heaai 6 x 1 x x 2 2 *2 *31100001000001010 str2_aut *7 6 x 1 x x 0 3 *2 *31100001000000011 str2_autai *7 6 x 1 x x 2 3 *2 *31100001000001011 nop 7 x x x x x x *11110000000000000
6-6 preliminary gigabitcam ke5bgca128 *1 the command is executable for all devices (a device cannot be selected). *2 only the device with empty priority accepts the command. *3 the command is not executed when the selected device does not have an empty entry. *4 the command is executable for all devices (but not usually used ). *5 only the device with a single hit priority accepts the command. *6 only the selected device with a single hit accepts the command. the command is not executed when there is a multi-hit or no hit in the device. *7 when the search result is a hit, the mask register which is used in the write to the address indicated by hha is determined by str1_hha/str2_hha in the cntl register. when the search result is no hit, the mask register which is used in the write to the address indicated by hea is determined by str1_hea/str2_hea in the cntl register although the mask register is selected by the external pin (gcms of the cntl1 register is 1). table 6.2 command format and conditions for execution (cont'd)
7-1 preliminary gigabitcam ke5bgca128 7. register descriptions 7.1 overview most of the registers of this device are 64 bits in width. the 32 bits on the msb side are assigned to the high side, and the 32 bits on the lsb side are assigned to the low side. registers are classified into six functional groups (com- mand register group, control status register group, memory r/w register group, configuration register group, comparand register group, and table status regis- ter group). an overview of each register group is presented below. (1) command register group this group has only one register, the com register, which is used to execute commands by writing the op-code (refer to chapter 6). (2) control register group this group has three registers, the cntl1, the cntl2, and the devid registers. the cntl1 register specifies the defi- nition of the mask register selection, the operation of the access and permanent bit, the endian, and the input mode. the cntl2 register specifies the output latency of the out- put port. the devid register is used to store the device id in a cascaded system. (3) memory r/w register group this group has ten registers: the devsel, the ar, the memar, the memarai, the memar_at, the memhha, the memhha_at, the memhea, the memheaai, and the memhea_at registers. the devsel register is used to select the device in a cascaded system. the ar register is used to specify the absolute address used for the read/write operation of the memar register. the memar register is used to read/write the con- tents of the cam table indicated by the ar register. the memarai register is used for automatic increment opera- tion of one ar register after it is accessed. the memar_at register is used to read/write the attribute data stored in the address indicated by the ar register. the memhha register is used to read/write the data stored in the address indicated by the hha register. the memhha_at register is used to read/write the attribute data stored in the address indicated by the hha register. the memhea register is used to read/write the data stored in the address indicated by the hea register. the memheaai register is used to automatically renew the hea register after it is accessed. the memhea_at regis- ter is used to read/write the attribute data stored in the ad- dress indicated by the hea register. (4) configuration register group this group has two types of registers, the mask registers and the sconf register. the mask registers set the mask pattern with a unit of one bit in the search operation or the write operation to the cam data. the sconf register de- fines the search configuration. (5) comparand register group this group has two registers, the cmp1 and the cmp2 reg- isters, each 64-bit wide. these registers are used for the search operation or the write operation, where the contents of these registers are written in the entry. (6) table status register group this group has two registers, the hha and the hea regis- ters. the hha register is used to store the hit address with the highest priority. the hea is used to store the empty address with the highest priority.
7-2 preliminary gigabitcam ke5bgca128 7.2 register addresses table 7.2.1 shows the register addresses. table 7.2.1 register address group register name address group register name address (1)command coml 00h (4)configuration mask2l 20h 01h mask2h 21h (2)con trol s tatu s cntl1l 02h mask3l 22h cntl1h 03h mask3h 23h cntl2l 04h mask4l 24h 05h mask4h 25h devidl 06h mask5l 26h devidh 07h mask5h 27h (3)memo ry r/w devsell 08h mask6l 28h 09h mask6h 29h arl 0ah mask7l 2ah 0bh mask7h 2bh memarl 0ch mask8l 2ch memarh 0dh mask8h 2dh memarail 0eh mask9l 2eh memaraih 0fh mask9h 2fh memar_ atl 10h mask10l 30h 11h mask10h 31h memhhal 12h mask11l 32h memhhah 13h mask11h 33h memhha_ atl 14h sconfl 36h 15h sconfh 37h memheal 16h (5)comparand cmp1l 38h memheah 17h cmp1h 39h memheaail 18h cmp2l 3ah memheaaih 19h cmp2h 3bh memhea_ atl 1ah (6)table s tatu s hhal 3ch 1bh 3dh (4)configuration mask0l 1ch heal 3eh mask0h 1dh 3fh mask1l 1eh mask1h 1fh
7-3 preliminary gigabitcam ke5bgca128 7.3 register bit maps (1) command register group com (command) register coml: add<5:0> = 00h each command is executed by writing the op-code in the 16 bits of the lsb side of this register. see chapter 6 for details of command op-code/function/execution condition. this register is only allowed to write. coml reg is ter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 op15 op14 op13 op12 op11 op10 op9 op8 op7 op6 op5 op4 op3 op2 op1 op0 bits name function after rstn(srst) 15-0 op<15:0> op-code(16-bit) unknown
7-4 preliminary gigabitcam ke5bgca128 (2) control status register group cntl1 (control1) register cntl1l : add<5:0> = 02h, cntl1h: add<5:0> = 03h this 64-bit register specifies the definition of the mask registers, the value of the permanent and access bits in the write operation by the memar or the memhea registers, the input mode, and the endian control of the automatic increment function. cntl1h reg is ter 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 hepm heac arpm arac gdms dhe3 dhe2 dhe1 dhe0 dhh3 dhh2 dhh1 dhh0 dar3 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 da r2 da r1 da r0 gcms che23 che22 che21 che20 chh23chh22 chh21chh20 ca r23ca r22 ca r21 ca r20 cntl1l reg is ter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 che13 che12 che11 che10 chh13chh12 chh11chh10 car13 car1 2 car11 car1 0 gbm s gb23 gb22 gb21 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gb20 gb13 gb12 gb11 gb10 gam s ga23 ga22 ga21 ga20 ga13 ga12 ga11 ga10 aisl dsl bits name function after rstn(srst) 61 hepm sets the permanent bit when writing m em hea or m em heaai, executing str1_ 0 hea or str2_hea, or executing str1_aut or str2_aut after the last search result is no hit. 60 heac sets the access bit when writing m em hea or m em heaai, executing 0 str1_hea or str2_hea, or executing str1_aut or str2_aut after the last search result is no hit. 59 arpm sets the permanent bit when writing m em ar or m em arai, or executing 0 str1_ar or str2_ar. 58 arac sets the access bit when writing m em ar or m em arai, or executing str1_ar or str2_ar. 0 gdm s selection method of the m ask registers in group d 57 0 group d is designated by the external pin, m s<3:0> 0 1 group d is designated by the control register. 56-53 dhe<3:0> designates the m ask register when writing table by m em hea or m em heaai. 0000 52-49 dhh<3:0> designates the m ask register when writing table by m em hha. 0000 48-45 dar<3:0> designates the m ask register when writing table by m em ar or m em arai. 0000
7-5 preliminary gigabitcam ke5bgca128 bits name function after rstn(srst) gcms selection method of the m ask registers in group c 44 0 group c is designated by the external p in, m s<3:0> 0 1 group c is designated by the control register. however, the m ask register is designated according to che1<3:0> or che2<3:0> when executing str1_aut or str2_aut after the last search result is no hit. 43-40 che2<3:0> designates the m ask register when writing a table by str2_hea, or designates the m ask register when executing str2_aut after the last search result is no hit. 0000 39-36 chh2<3:0> designates the m ask register when writing a table by str2_hha, or designates the m ask register when executing str2_aut after the last search result is a hit. 0000 35-32 car2<3:0> designates the m ask register when writing a table by str2_ar. 0000 31-28 che1<3:0> designates the m ask register when writing a table by str1_hea, or designates the m ask register when executing str1_aut after the last search result is no hit. 0000 27-24 chh1<3:0> designates the m ask register when writing a table by str1_hha, or designates the m ask register when executing str1_aut after the last search result is a hit. 0000 23-20 car1<3:0> designates the m ask register when writing a table by str1_ar. 0000 gbms selection method of the m ask registers in group b 19 0 group b is designated by the external p in, m s<3:0>. 0 1 group b is designated by the control register. 18-15 gb2<3:0> designates the m ask register when searching by the srch2 command. 0000 14-11 gb1<3:0> designates the m ask register when searching by the srch1 command 0000 gams selection method of the m ask registers in group a 10 0 group a is designated by the external pin, m s<3:0>. 0 1 group a is designated by the control register. 9-6 ga2<3:0> designates the m ask register when searching by cm p2 and the srchn pin. 0000 5-2 ga1<3:0> designates the m ask register when searching by cm p1 and the srchn pin. 0000
7-6 preliminary gigabitcam ke5bgca128 bits name function after rstn(srst) 1 aisl sets the address increment condition in writing the m em arai or m em heaai registers when dat<31:0> input is 32-bit mode, or in reading the m em arai or m em heaai registers. 0 0 access to the low side 1 access to the high side dsl register access m ethod 0 the data is stored in the buffer of the device when the phase signal is "0" and then is written in the registers with a unit of 32 bits. (when 32 bits on the high/low side of m em ar, m em arai, m em hha, m em hea, or m em heaai is written, the other 32 bits on the low/high side is masked. (the access, permanent, or empty bits are set by the write operation of only the half side, 32 bits.) 0 1 the registers in the device are written with a unit of 64 bits. (when the phase signal is "1," 32 bits on the high side is stored in the buffer. when the phase signal changes to "0," 32 bits on the low side is stored in the buffer. then, the high side 0 and the low side are combined to 64 bits and written in the registers.) (the least bit of add<5:0> is ignored (don't care) and the data is written with a unit of 64 bits.)
7-7 preliminary gigabitcam ke5bgca128 cntl2 (control2) register cntl2l : add<5:0> = 04h this register specifies the latency of hha, memhha, and shon. it is prohibited to modify-write the cntl2 register right after the search operation. four nop commands or an 8 clock wait must be inserted after the search operation. cntl2l reg is ter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mem l hol outl1outl0 (*1) when hha/hea latency = 4, invalid flag (bit15 of od port) is unknown. therefore, this flag can not be used to confirm whether the output hha is invalid (multi-hit result) or not. the smon signal (latency =5) indicates whether the search result is multi-hit or not. bits name function after rstn(srst) m em l output port: defines the latency of m em hha outp ut 3 0 latency = 6 0 1 latency = 7 hol shon latency : defines the latency of shon 2 0 latency = 4 0 1 latency = 5 outl<1:0> output port: defines the latency of hha/hea output. 00 latency =5 1-0 01 latency =6 00 10 latency =7 11 latency =4 (*1)
7-8 preliminary gigabitcam ke5bgca128 devid register devidl : add<5:0>= 06h, devidh : add<5:0>= 07h this register stores the number of each device (device id) for the operation of a cascaded system. it is necessary to access this register and to set the unique device id for each device in a cascaded system after each device reset opera- tion. the ld bit of the last device must be set to 1, and that of other devices must be set to 0. the ld is set to 1 when a low pulse is given to the rstn pin, or the srst command is issued. it is not necessary to write the ld bit in a single device system, but the ld bit must be set to 1 if the device id is written. this register is allowed to read/ write only in the devid mode. devidh register 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 devidl register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ld di4 di3 di2 di1 di0 bits name function after rstn(srst) ld last device flag 15 0 not last device 1 1 last device 4-0 di<4:0> device id 00000
7-9 preliminary gigabitcam ke5bgca128 (3) memory r/w register group devsel register devsell : add<5:0>= 08h this register selects and accesses specific devices (device select) in a cascaded system. the br bit is set to 1, which means accessing all devices (broadcast) immediately after the device reset operation. when accessing only one spe- cific device, it is necessary to write br = 0 (not broadcast) and the device id which the user wishes to select in the ds<4:0> bits in this register. d evs ell re g is t e r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 br ds4 ds3 ds2 ds1 ds0 bits name function after rstn(srst) br broadcast flag 15 0 not broadcast 1 1 broadcast 4-0 ds<4:0> device id to be accessed 00000
7-10 preliminary gigabitcam ke5bgca128 ar register arl : add<5:0>= 0ah this register specifies the absolute address that is used for accessing the cam by the memar register. the data writ- ten in this register (00000000h ~ 000007ffh) is the absolute address of the cam. it is possible to read/write the stored data of the cam specified by the absolute address by first writing the absolute address in this register then executing a read/write operation of the memar register. arl register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ar10 ar9 ar8 ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 bits name function after rstn(srst) 10-0 ar<10:0> absolute address of the cam table 00000000000
7-11 preliminary gigabitcam ke5bgca128 memar register memarl : add<5:0>= 0ch, memarh : add<5:0>=0dh this 64-bit register operates as a port for accessing the entry data of the cam indicated by the ar register. when the entry data is accessed, 0 is input in the empty bit and the value defined by the cntl1 register is input in the perma- nent and access bits. memarh register 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 ma63 ma62 ma61 ma60 ma59 ma58 ma57 ma56 ma55 ma54 ma53 ma52 ma51 ma50 ma49 ma48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 ma47 ma46 ma45 ma44 ma43 ma42 ma41 ma40 ma39 ma38 ma37 ma36 ma35 ma34 ma33 ma32 memarl register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ma31 ma30 ma29 ma28 ma27 ma26 ma25 ma24 ma23 ma22 ma21 ma20 ma19 ma18 ma17 ma16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ma15 ma14 ma13 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 bits name function after rstn(srst) 63-0 m a<63:0> entry data indicated by the ar register unknown emp ty bit : "0" is inp ut. permanent bit : the value defined by the cntl1 register is input. access bit : the value defined by the cntl1 register is inp ut.
7-12 preliminary gigabitcam ke5bgca128 memarai register memarail : add<5:0>= 0eh, memaraih : add<5:0>= 0fh this 64-bit register operates as a port for accessing the en- try data of the cam indicated by the ar register. when the entry data is accessed, 0 is input in the empty bit and the value defined by the cntl1 register is input in the perma- nent and access bits. the increment operation of the ar register is executed when this register is accessed. this op- eration is executed by access to this register in the 64-bit input mode. it is also executed by access to either the low side or the high side according to the definition of the endian of the cntl1 register in the 32-bit input mode and the read operation. memaraih register 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 ma63 ma62 ma61 ma60 ma59 ma58 ma57 ma56 ma55 ma54 ma53 ma52 ma51 ma50 ma49 ma48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 ma47 ma46 ma45 ma44 ma43 ma42 ma41 ma40 ma39 ma38 ma37 ma36 ma35 ma34 ma33 ma32 memarail register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ma31 ma30 ma29 ma28 ma27 ma26 ma25 ma24 ma23 ma22 ma21 ma20 ma19 ma18 ma17 ma16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ma15 ma14 ma13 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 bits name function after rstn(srst) 63-0 m a<63:0> entry data indicated by the arai register unknown emp ty bit : "0" is inp ut. permanent bit : the value defined by the cntl1 register is input. access bit : the value defined by the cntl1 register is inp ut.
7-13 preliminary gigabitcam ke5bgca128 memar_at register memar_atl : add<5:0>= 10h this 64-bit register operates as a port for accessing the at- tribute data of the entry in the cam indicated by the ar register. bits name function after rstn(srst) msem emp ty bit m ask 5 0 em is written in the empty bit. unknown 1 no change in the empty bit 4 em emp ty bit data unknown mspm permanent bit m ask 3 0 pm is written in the permanent bit. unknown 1 no change in the permanent bit 2 pm permanent bit data unknown msac access bit mask 1 0 ac is written in the access bit. unknown 1 no change in the access bit 0 ac access bit data unknown memar_atl register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msem em mspm pm msac ac
7-14 preliminary gigabitcam ke5bgca128 memhha register memhhal : add<5:0>= 12h, memhhah : add<5:0>= 13h this 64-bit register operates as a port for accessing the en- try data of the cam indicated by the hha register. even if the entry data is modified-written by this register, the empty, permanent, and access bits of the entry do not change. memhhal register 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 ma63 ma62 ma61 ma60 ma59 ma58 ma57 ma56 ma55 ma54 ma53 ma52 ma51 ma50 ma49 ma48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 ma47 ma46 ma45 ma44 ma43 ma42 ma41 ma40 ma39 ma38 ma37 ma36 ma35 ma34 ma33 ma32 memhhah register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ma31 ma30 ma29 ma28 ma27 ma26 ma25 ma24 ma23 ma22 ma21 ma20 ma19 ma18 ma17 ma16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ma15 ma14 ma13 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 bits name function after rstn(srst) 63-0 m a<63:0> entry data indicated by the hha register unknown the emp ty, permanent, and access bits do not change.
7-15 preliminary gigabitcam ke5bgca128 memhha_at register memhha_atl : add<5:0>= 14h this 64-bit register operates as a port for accessing the at- tribute data of the entry in the cam indicated by the hha register. memhha_atl register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msem em mspm pm msac ac bits name function after rstn(srst) msem emp ty bit m ask 5 0 em is written in the empty bit. unknown 1 no change in the empty bit 4 em emp ty bit data unknown mspm permanent bit m ask 3 0 pm is written in the permanent bit. unknown 1 no change in the permanent bit 2 pm permanent bit data unknown msac access bit mask 1 0 ac is written in the access bit. unknown 1 no change in the access bit 0 ac access bit data unknown
7-16 preliminary gigabitcam ke5bgca128 memhea register memheal : add<5:0>= 16h, memheah : add<5:0>= 17h this 64-bit register operates as a port for accessing the en- try data of the cam indicated by the hea register. when the entry data is accessed, 0 is input in the empty bit and the value defined by the cntl1 register is input in the per- manent and access bits. memheah register 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 ma63 ma62 ma61 ma60 ma59 ma58 ma57 ma56 ma55 ma54 ma53 ma52 ma51 ma50 ma49 ma48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 ma47 ma46 ma45 ma44 ma43 ma42 ma41 ma40 ma39 ma38 ma37 ma36 ma35 ma34 ma33 ma32 memheal register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ma31 ma30 ma29 ma28 ma27 ma26 ma25 ma24 ma23 ma22 ma21 ma20 ma19 ma18 ma17 ma16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ma15 ma14 ma13 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 bits name function after rstn(srst) 63-0 m a<63:0> entry data indicated by the hea register unknown emp ty bit : "0" is inp ut. permanent bit : the value defined by the cntl1 register is input. access bit : the value defined by the cntl1 register is inp ut.
7-17 preliminary gigabitcam ke5bgca128 memheaai register memheaail : add<5:0>= 18h, memheaaih : add<5:0>= 19h this 64-bit register operates as a port for accessing the en- try data of the cam indicated by the hea register. when the entry data is accessed, 0 is input in the empty bit and the value defined by the cntl1 register is input in the per- manent and access bits. the renew operation of the hea register is executed when this register is accessed. this op- eration is executed by access to this register in the 64-bit input mode. it is also executed by access to either the low side or the high side according to the definition of the endian of the cntl1 register in the 32-bit input mode. memheaaih register 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 ma63 ma62 ma61 ma60 ma59 ma58 ma57 ma56 ma55 ma54 ma53 ma52 ma51 ma50 ma49 ma48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 ma47 ma46 ma45 ma44 ma43 ma42 ma41 ma40 ma39 ma38 ma37 ma36 ma35 ma34 ma33 ma32 memheaail register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ma31 ma30 ma29 ma28 ma27 ma26 ma25 ma24 ma23 ma22 ma21 ma20 ma19 ma18 ma17 ma16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ma15 ma14 ma13 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma53 ma4 ma35 ma2 ma1 ma0 bits name function after rstn(srst) 63-0 m a<63:0> entry data indicated by the hea register unknown emp ty bit : "0" is inp ut. permanent bit : the value defined by the cntl1 register is input. access bit : the value defined by the cntl1 register is inp ut.
7-18 preliminary gigabitcam ke5bgca128 memhea_at register memhea_atl : add<5:0>= 1ah this 64-bit register operates as a port for accessing the at- tribute data of the entry in the cam indicated by the hea register. memhea_atl register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msem em mspm pm msac ac bits name function after rstn(srst) msem emp ty bit m ask 5 0 em is written in the empty bit. unknown 1 no change in the empty bit 4 em emp ty bit data unknown mspm permanent bit m ask 3 0 pm is written in the permanent bit. unknown 1 no change in the permanent bit 2 pm permanent bit data unknown msac access bit data 1 0 ac is written in the access bit. unknown 1 no change in the access bit 0 ac access bit data unknown
7-19 preliminary gigabitcam ke5bgca128 (4) configuration register group mask(0~11) register mask0l : add<5:0>= 1ch, mask0h : add<5:0>= 1dh, mask1l : add<5:0>= 1eh, mask1h : add<5:0>= 1fh, mask2l : add<5:0>= 20h, mask2h : add<5:0>= 21h, mask3l : add<5:0>= 22h, mask3h : add<5:0>= 23h, mask4l : add<5:0>= 24h, mask4h : add<5:0>= 25h, mask5l : add<5:0>= 26h, mask5h : add<5:0>= 27h, mask6l : add<5:0>= 28h, mask6h : add<5:0>= 29h, mask7l : add<5:0>= 2ah, mask7h : add<5:0>= 2bh, mask8l : add<5:0>= 2ch, mask8h : add<5:0>= 2dh, mask9l : add<5:0>= 2eh, mask9h : add<5:0>= 2fh, mask10l : add<5:0>= 30h, mask10h : add<5:0>= 31h, mask11l : add<5:0>= 32h, mask11h : add<5:0>= 33h mask(0~11)h regis ter 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 ms63 ms62 ms61 ms60 ms59 ms58 ms57 ms56 ms55 ms54 ms53 ms52 ms51 ms50 ms49 ms48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 ms47 ms46 ms45 ms44 ms43 ms42 ms41 ms40 ms39 ms38 ms37 ms36 ms35 ms34 ms33 ms32 mask(0~11)l regis ter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ms31 ms30 ms29 ms28 ms27 ms26 ms25 ms24 ms23 ms22 ms21 ms20 ms19 ms18 ms17 ms16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ms15 ms14 ms13 ms12 ms11 ms10 ms9 ms8 ms7 ms6 ms5 ms4 ms3 ms2 ms1 ms0 there are 12, 64-bit mask registers. each register represents a different set of mask data . each mask register can be set for the search configuration respectively by the sconf reg- ister. the value of these registers after initialization is un- known. bits name function after rstn(srst) 63-0 m s<63:0> defines the m ask register. unknown
7-20 preliminary gigabitcam ke5bgca128 sconfh register 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 as11 he11 m h11 s11<1:0> as10 he10 m h10 s10<1:0> as09 he09 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 m h09 s09<1:0> as08 he08 m h08 s08<1:0> as07 he07 m h07 s07<1:0> as06 he06 m h06 sconfl register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 s06<1:0> as05 he05 m h05 s05<1:0> as04 he04 m h04 s04<1:0> as03 he03 m h03 s03<1> 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s03<0> as02 he02 m h02 s02<1:0> as01 he01 m h01 s01<1:0> as00 he00 m h00 s00<1:0> sconf (search configuration) register sconfl : add<5:0>= 36h, sconfh : add<5:0>= 37h this register sets the search configuration for 12 respective mask registers, such as setting the access bit to 0 or 1 when the search result is a hit and setting the output operation for the output port. bits name function after rstn(srst) as* indicates whether the access bit which is hit is set to "1" or not. 59-4 0 not set 0 1set he* indicates whether hea is outp ut or not in a no hit case. 58-3 0 no output 0 1 outp ut m h* indicates whether the 16-bit fragment of mem hha is outp ut or not. 57-2 0 no output 0 1 outp ut s*<1:0> when outp utting m em hha, designates which 16-bit fragment of 64 bits to be out p ut. 00 m em hha<15:0> 00 56-0 01 m em hha<31:16> 10 m em hha<47:32> 11 m em hha<63:48> *: 00~11
7-21 preliminary gigabitcam ke5bgca128 cmp 1/2h reg is ter 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 cp63 cp62 cp61 cp60 cp59 cp58 cp57 cp56 cp55 cp54 cp53 cp52 cp51 cp50 cp49 cp48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 cp47 cp46 cp45 cp44 cp43 cp42 cp41 cp40 cp39 cp38 cp37 cp36 cp35 cp34 cp33 cp32 cmp 1/2l reg is ter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 cp31 cp30 cp29 cp28 cp27 cp26 cp25 cp24 cp23 cp22 cp21 cp20 cp19 cp18 cp17 cp16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cp15 cp14 cp13 cp12 cp11 cp10 cp9 cp8 cp7 cp6 cp5 cp4 cp3 cp2 cp1 cp0 (5) comparand register group cmp1/2 register cmp1l : add<5:0>= 38h, cmp1h : add<5:0>= 39h, cmp2l : add<5:0>= 3ah, cmp2h : add<5:0>= 3bh there are two 64-bit comparand registers which can be used for the search operation and whose content can be written in the entry. when the srchn is active in the write opera- bits name function after rstn(srst) 63-0 cp<63:0> definition of the cm p register all 0 tion to these registers, the search operation in the cam is executed simultaneously.
7-22 preliminary gigabitcam ke5bgca128 (6) table status register group hha (highest hit address) register hhal : add<5:0>= 3ch this register stores the entry address of the hit entry after a search operation. when there is a single hit in a cascaded system, the hv flag is set to 0, and the syh flag is set to 1. in other cases in a cascaded system, the hv flag is set to 1, and the syh flag is set to 0. in the ld bit, the last device flag of the devsel register of the device with single hit priority is output. when there is a multi-hit in a cascaded system, the sym flag is set to 1. when there is a single hit in a device, the ht flag is set to 1. when there is a multi-hit in a device, the mh flag is set to 1. sye is the empty flag of the cascaded system. the device id of the device with single hit priority is output in di<4:0>. this register is al- lowed only to read in all modes. hhal register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 hv ld syh sym ht mh sye di4 di3 di2 di1 di0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ha10 ha9 ha8 ha7 ha6 ha5 ha4 ha3 ha2 ha1 ha0 bits name function after rstn(srst) hv single hit address valid flag 31 0 valid 1 1 invalid 30 ld last device flag 1 syh single hit flag in the cascaded sy stem 29 0 no single hit 0 1 single hit sym m ulti-hit flag in the cascaded system 28 0 no m ulti-hit 0 1 m ulti-hit ht single hit flag in the device 27 0 no single hit 0 1 single hit m h m ulti-hit flag in the device 26 0 no m ulti-hit 0 1 m ulti-hit sye emp ty flag in the cascaded system 25 0 no emp ty entry 1 1 empty entry 20-16 di<4:0> device id 00000 10-0 ha<10:0> highest hit address all 0
7-23 preliminary gigabitcam ke5bgca128 hea (highest empty address) register heal : add<5:0>= 3eh this register stores the entry address with the highest empty priority among the empty entries. when there is no empty address, the ev flag is set to 1. the last device flag of the devsel register of the device with empty priority is output in the ld bit. syh and sym are set in the same way as in the hha register. sye is the empty flag in the cas- caded system. et is the empty flag in the device. heal register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ev ld syh sym sye et di4 di3 di2 di1 di0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 he10 he9 he8 he7 he6 he5 he4 he3 he2 he1 he0 bits name function after rstn(srst) ev highest emp ty address valid flag 31 0 valid 1 1 invalid 30 ld last device flag 1 syh single hit flag in the cascaded sy stem 29 0 no single hit 0 1 single hit sym m ulti-hit flag in the cascaded system 28 0 no multi-hit 0 1 m ulti-hit sye emp ty flag in the cascaded system 25 0 no empty entry 1 1 emp ty entry et emp ty flag in the device 24 0 no empty entry 1 1 emp ty entry 20-16 di<4:0> device id 00000 10-0 he<10:0> highest empty address all 0
7-24 preliminary gigabitcam ke5bgca128 7.4 conditions for accessing registers table 7.4.1 conditions for accessing registers table 7.4.1 shows conditions for accessing registers. broadcast device s el ect name r/w address<5:0> writ e read out put device writ e read coml exis t w 00h x no device *1 x comh not exist 01h cntl1l exis t r/w 02h last device *1 cntl1h exis t r/w 03h last device *1 cntl2l exis t r/w 04h last device *1 cntl2h not exist 05h devidl exis t r/w 06h devid priority device x x devidh not exist 07h devsell exis t r/w 08h last device *1 devselh not exist 09h arl exis t r/w 0ah last device *1 arh not exist 0bh memarl exis t r/w 0ch *2 last device memarh exis t r/w 0dh *2 last device memarail exis t r/w 0eh *2 last device memaraih exis t r/w 0fh *2 last device memar_atl exis t r/w 10h *2 last device memar_ath not exist 11h memhhal exis t r/w 12h *3 hit priorit y device *4 *5 *6 memhhah exis t r/w 13h *3 hit priorit y device *4 *5 *6 memhha_atl exis t r/w 14h *3 hit priorit y device *4 *5 *6 memhha_ath not exist 15h memheal exis t r/w 16h *7 empty priority device *8 *9 *10 memheah exis t r/w 17h *7 empty priority device *8 *9 *10 memheaail exis t r/w 18h *7 empty priority device *8 *9 *10 memheaaih exis t r/w 19h *7 empty priority device *8 *9 *10 memhea_atl exis t r/w 1ah *7 empty priority device *8 *9 *10 memhea_ath not exist 1bh
7-25 preliminary gigabitcam ke5bgca128 : allowed : allowed but not selectable x : not allowed table 7.4.1 conditions for accessing registers (cont'd) broadcast device s el ect name r/w address<5:0> writ e read out put device writ e read mask0l exis t r/w 1ch last device mask0h exis t r/w 1dh last device mask1l exis t r/w 1eh last device mask1h exis t r/w 1fh last device mask2l exis t r/w 20h last device mask2h exis t r/w 21h last device mask3l exis t r/w 22h last device mask3h exis t r/w 23h last device mask4l exis t r/w 24h last device mask4h exis t r/w 25h last device mask5l exis t r/w 26h last device mask5h exis t r/w 27h last device mask6l exis t r/w 28h last device mask6h exis t r/w 29h last device mask7l exis t r/w 2ah last device mask7h exis t r/w 2bh last device mask8l exis t r/w 2ch last device mask8h exis t r/w 2dh last device mask9l exis t r/w 2eh last device mask9h exis t r/w 2fh last device mask10l exis t r/w 30h last device mask10h exis t r/w 31h last device mask11l exis t r/w 32h last device mask11h exis t r/w 33h last device sconfl exis t r/w 36h last device sconfh exis t r/w 37h last device cmp1l exis t r/w 38h last device cmp1h exis t r/w 39h last device cmp2l exis t r/w 3ah last device cmp2h exis t r/w 3bh last device hhal exis t r 3ch x hit priorit y device *4 x *6 hhah not exis t 3dh heal exis t r 3eh x empty priorit y device *8 x *10 heah not exis t 3fh
7-26 preliminary gigabitcam ke5bgca128 *1 the write operation is executed for all devices. (it is not possible to specify the device.) *2 the write operation is executed for all devices (but not usually used ). *3 the write operation is executed only in the device with a single hit. (i.e. no write operation in the device with a multi-hi t or no hit) when there is a multi-hit in the simple cascaded system, the write operation is executed in the device with the highest hit priority among devices excluding the one with a multi-hit. *4 the device with a single hit outputs the data. (the device with a multi-hit or no hit does not output the data.) when there is a multi-hit in the simple cascaded system, the device with the highest single hit priority among devices, excluding the one with a multi-hit, outputs the data. however, it is necessary that hit priority is propagated. when there is no device with a single hit in the system, the last device outputs invalid data. *5 the write operation is not executed when there is a multi-hit or no hit in the selected device. *6 invalid data is output when there is a multi-hit or no hit in the selected device. *7 the write operation is not executed when there is no device with empty priority. (i.e. write operation is executed only in the device with empty priority.) *8 data is output from the device with empty priority. (when there is no device with empty priority in the cascaded system, the last device outputs invalid data.) *9 the write operation is not executed when the selected device does not have empty entry. *10 invalid data is output when the selected device does not have empty priority. table 7.4.1 conditions for accessing registers (cont'd)
8-1 preliminary gigabitcam ke5bgca128 8. package/ordering information 8.1 ordering information the ke5bgca128 product is available in two kinds of package according to users environment as follows. consult the local kawasaki lsi sales office to order. part number package KE5BGCA128ACFP dph sqfp128 *1 ke5bgca128bcfp sqfp128 *1 dph (die pad heat spreader) thermal resistance of the dph sqfp128 package is less than the sqfp128 package.
8-2 preliminary gigabitcam ke5bgca128 8.2 package drawing the drawing of the dph sqfp128 package and the drawing of the sqfp128 package are identical as follows. unit: mm 39 64 65 102 103 128 20.00 typ 23.20 0.25 14.00 typ 17.20 0.25 1 38 0.20 0.50 0.08 0.80 0.20 0.38 0.13 2.70typ 3.55 max +0.07 -0.02 0 ~10 0.70 typ 1.60 typ 0.17 +0.03 -0.07
9-1 preliminary gigabitcam ke5bgca128 9. electrical characteristics *1 input/output pins are not 5v tolerant i/o pins. 9.1 absolute maximum rating 9.2 operating range 9.3 dc characteristics item symbol min. typ. max. unit supply voltage v dd 3.0 3.3 3.6 v ambient operating temperature t a 0+25+70 c item symbol standard condition unit note supply voltage v dd -0.3 ~ 4.0 v input voltage v i -0.3 ~ v dd + 0.3 v * 1 output voltage v o -0.3 ~ v dd + 0.3 v * 1 i/o voltage v io -0.3 ~ v dd + 0.3 v * 1 storage temperature t st g -40 ~ +125 c *2 in case of flon, phon, pmon pins : iol = 4ma, -4ma other output pins : iol = 8ma, -8ma item symbol min. typ. max. unit condition input low voltage v il 0.8 v input high voltage v ih 2.0 v output low voltage v ol 0.4 v iol = 8ma, 4ma * 2 output high voltage v oh 2.4 v ioh = -8ma, -4ma *2 input leakage current i il -10 a vin = gnd i ih 10 a vin = v dd output leakage current i oz -10 10 a output is high impedance standby current i dds 250 a dynamic operating current i ddop 500 ma
9-2 preliminary gigabitcam ke5bgca128 t a = 0 ~ 70 c, v dd = 3.3 v 0.3v 9.4 ac characteristics *1 when the operation which needs priority determination falls under one of the cases shown below, the setup/hold time must be counted from 3 clock after the input operation . 1) memhha (read/write) 2) memhea (read/write), memheaai (read/write) 3) str1_hha, str2_hha command 4) str1_hea, str2_hea, str1_heaai, str2_heaai command 5) str1_aut, str2_aut, str1_autai, str2_autai command *1 when the operation which needs priority determination is hha or hea (read) operation, the setup/hold time must be counted from 5 clock after the input operation . see fig. 9.4.1. no. parameter min max unit note 1 clk cycle time 15 ns 2 clk width high 5 ns 3 clk width low 5 ns 4 dat<31:0> setup time to clk 3 ns 5 dat<31:0> ho ld time after clk 1 n s 6 add<5:0> setup time to clk 3 ns 7 add<5:0> hold time after clk 1 ns 8 phase setup time to clk 3 ns 9 phase hold time after clk 1 ns 10 srchn setup time to clk 3 ns 11 srchn h old time after clk 1 n s 12 rwn setup time to clk 3 ns 13 rwn hold time after clk 1 ns 14 cen setup time to clk 3 ns 15 cen hold time after clk 1 ns 16 ms<3:0> setup time to clk 3 ns 17 ms<3:0> ho ld time after clk 1 n s 18 oedatn setup time to clk 3 ns 19 oedatn hold time after clk 1 ns 20 oeodn setup time to clk 3 ns 21 oeodn hold time after clk 1 ns 22 opsl setup time to clk 8 ns 23 opsl hold time after clk 1 ns 24 phin setup time to clk 3 ns *1 25 phin hold time after clk 3 ns *1 26 pmin setup time to clk 1 3 ns *1 27 pmin hold time after clk 1 3 ns *1
9-3 preliminary gigabitcam ke5bgca128 *1a when the operation which needs priority determination is nxt_pr command operation, the setup/hold time must be counted from 2 clock after the input operation . see fig. 9.4.1. *2 counted from clk when phase is low. latency must be added. see fig. 9.4.2. *3 shon and smon transition by the srst command. see fig. 9.4.3. *4 when the operation which changes the priority falls under one of the cases shown below, this must be counted from 3 clock after operation input. see fig. 9.4.4. 1) search operation by the srchn pin 2) search operation by the srch command 3) memheaai (read/write) 4) execution of the nxt_hea, gen_fl, str1_heaai, str2_heaai, str1_autai, or str2_autai commands *5 phon, pmon and flon transition from high to low by the srst command. see fig. 9.4.5. *6 pmon transition by the str_dev, end_dev, or nxt_pr commands. see fig. 9.4.6. no. parameter min max unit note 28 pmin setup time to clk 2 3 ns *1a 29 pmin hold time after clk 2 2 ns *1a 30 flin setup time to clk 3 ns *1 31 flin hold time after clk 3 ns *1 32 clk high to dat<31:0> activ e 17 n s * 2 33 dat<31:0> valid fro m clk 20 n s * 2 34 dat<31:0> ho ld after clk 3 n s * 2 35 clk high to od<20:0> activ e 17 n s * 2 36 od<20:0> v alid from clk 20 n s * 2 37 od<20:0> h old after clk 3 n s * 2 38 clk high to shon active 1 16 ns *2 39 clk high to smon active 1 16 n s * 2 40 clk high to shon active 2 16 ns *3 41 clk high to smon active 2 16 ns *3 42 clk high to phon active 1 65 ns *4 43 clk high to phon inactive 1 5 ns *4 44 clk high to pmon active 1 65 ns *4 45 clk high to pmon inactive 1 5 ns *4 46 clk high to flon active 1 55 ns *4 47 clk high to flon inactive 1 5 ns *4 48 clk high to phon active 2 50 ns *5 49 clk high to phon inactive 2 5 ns *5 50 clk high to pmon active 2 50 ns *5 51 clk high to pmon inactive 2 5 ns *5 52 clk high to pmon active 3 25 ns *6 53 clk high to pmon inactive 3 4 ns *6 54 clk high to flon active 2 50 ns *5 55 clk high to flon inactive 2 5 ns *5
9-4 preliminary gigabitcam ke5bgca128 test loads note: characteristics are measured under the following conditions: input "h" level 3.3 v input "l" level 0.0 v input "h" reference voltage 1.5 v input signal through rate 1.0 ns/v output judgment level vdd/2 load capacitance (cl) 100 pf (dat<31:0>) load capacitance (cl) 50 pf (other than dat<31:0>) "h" level output loading current (ioh) -4 ma (flon, phon, pmon pins), -8ma (other pins) "l" level output loading current (iol) 4 ma (flon, phon, pmon pins), 8ma (other pins) dut c l i oh v dd /2 i ol no. parameter min max unit note 56 phin to phon active 18 n s 57 phin to pmon active 18 ns 58 pmin to pmon active 18 n s 59 flin to flon active 18 n s 60 rstn lo w to phon active 45 n s 61 rstn lo w t o pmon act iv e 45 n s 62 rstn lo w to flon active 45 n s 63 rstn width low 60 ns
9-5 preliminary gigabitcam ke5bgca128 fig. 9.4.1 setup/hold time count of phin, pmin, and flin operation o p eration in p ut cen clk phase 3 clocks 5 clocks phin, pmin, flin pmin setup hold setup hold setup hold 2 clocks
9-6 preliminary gigabitcam ke5bgca128 operation o p eration in p ut cen clk phase valid 6 clocks dat<31:0> ( latenc y = 4 ) hold time transition time low to active valid hold time transition time low to active od<20:0> ( when latenc y is 5 ) 8 clocks hold time shon ( when latenc y is 4 ) transition time 6 clocks fig. 9.4.2 output cycle of dat<31:0>, od<20:0>, shon, and smon
9-7 preliminary gigabitcam ke5bgca128 fig. 9.4.3 output cycle of shon and smon fig. 9.4.4 output cycle of phon, pmon, and flon operation 3 clocks srst command o p eration in p ut cen clk phase shon, smon 3 clocks rstn shon, smon transition time transition time hold time transition time o p eration in p ut cen clk phase phon, pmon, flon
9-8 preliminary gigabitcam ke5bgca128 operation input operation cen clk phase pmon 2 clocks transition time operation input operation cen clk phase phon, pmon, flon hold time 2 clocks transition time fig. 9.4.5 output cycle of phon, pmon, and flon fig. 9.4.6 output cycle of pmon
9-9 preliminary gigabitcam ke5bgca128 *1 necessary when the input mode is 64 bits. fig.9.4.7 (a) ac specifications clk phase dat<31:0> add<5:0>, srchn, rwn, cen, ms<3:0>, oedatn, oeodn, opsl phin, pmin, flin *1 *1 pmin 1 2 3 8 9 8 4 5 4 5 10 12 14 16 18 20 22 11 13 15 17 19 21 23 28 24 26 30 29 25 27 31
9-10 preliminary gigabitcam ke5bgca128 *1 when the read operation has finished, this is hi-z even if oedatn is 0. fig.9.4.7 (b) ac specifications (cont'd) clk phase dat<31:0> oedatn oeodn od<20:0> shon, smon valid valid valid valid phon, pmon, flon shon, smon *1 32 33 34 35 36 37 38 39 40 41 42 44 46 43 45 47
9-11 preliminary gigabitcam ke5bgca128 fig.9.4.7 (c) ac specifications (cont'd) phon flon clk phase pmon pmon 49 48 50 51 52 53 54 55
9-12 preliminary gigabitcam ke5bgca128 fig.9.4.7 (d) ac specifications (cont'd) phin, pmin, flin phon, pmon, flon rstn phon, pmon flon 63 60 61 56 57 58 59 62
kawasaki lsi reserves the right to make changes without further notice to any products herein to improve reliab ility, function or design. kawasaki lsi does not assume any liability arising out of the application or use of any p roducts or circuit described herein ; neither does it convey any license under its patent rights nor the rights of oth ers. kawasaki lsi products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other a pplication in which the failure of the kawasaki lsi products could create a situation where personal injury or death may occur. should buyer purchase or use kawasaki lsi products for any such unintended or unauthorized application, buyer shall indemnify and hold kawasaki lsi and its officers, employees subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that kawasaki lsi was negligent regarding the design or manufacture of the part. for more information or questions about kawasaki lsi cam products contact: kawasaki lsi u. s. a. inc. 2570 north first street, suite # 301, 501 edgewater dr., suite 510 san jose, ca 95131 wakefield, ma 01880 phone 408-570-0555 phone 617-224-4201 fax 408-570-0567 fax 617-224-2503 internet info@klsi.com or kawasaki steel corp. makuhari techno garden b5 1-3 nakase mihama-ku, chiba 261-01, japan phone 81-43-296-7432 fax 81-43-296-7419 internet klsi@lsidiv.kawasaki-steel.co.jp

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